A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

Hyun Woo Lee; Yong Hoon Kim; Won Joo Yun; Eun Young Park; Kang Youl Lee; Jaeil Kim; Kwang Hyun Kim; Jong Ho Jung; Kyung Whan Kim; Nam Gyu Rye; Kwan Weon Kim; Jun Hyun Chun; Chulwoo Kim; Young Jung Choi; Byong Tae Chung; Joong Sik Kih

doi:10.1109/ISCAS.2010.5537703

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

Hyun Woo Lee, Yong Hoon Kim, Won Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young Jung Choi, Byong Tae Chung, Joong Sik Kih

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	3861-3864
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537703
Publication status	Published - 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 2010 May 30 → 2010 Jun 2

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	10/5/30 → 10/6/2

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2010.5537703

Cite this

Lee, H. W., Kim, Y. H., Yun, W. J., Park, E. Y., Lee, K. Y., Kim, J., Kim, K. H., Jung, J. H., Kim, K. W., Rye, N. G., Kim, K. W., Chun, J. H., Kim, C., Choi, Y. J., Chung, B. T., & Kih, J. S. (2010). A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 3861-3864). Article 5537703 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537703

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. / Lee, Hyun Woo; Kim, Yong Hoon; Yun, Won Joo et al.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3861-3864 5537703 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, HW, Kim, YH, Yun, WJ, Park, EY, Lee, KY, Kim, J, Kim, KH, Jung, JH, Kim, KW, Rye, NG, Kim, KW, Chun, JH, Kim, C, Choi, YJ, Chung, BT & Kih, JS 2010, A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537703, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 3861-3864, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537703

Lee HW, Kim YH, Yun WJ, Park EY, Lee KY, Kim J et al. A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3861-3864. 5537703. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5537703

Lee, Hyun Woo ; Kim, Yong Hoon ; Yun, Won Joo et al. / A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 3861-3864 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

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abstract = "A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.",

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AU - Kim, Jaeil

AU - Kim, Kwang Hyun

AU - Jung, Jong Ho

AU - Kim, Kyung Whan

AU - Rye, Nam Gyu

AU - Kim, Kwan Weon

AU - Chun, Jun Hyun

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AB - A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.

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A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

Abstract

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ASJC Scopus subject areas

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