A 9-bit 500-MS/s 2-bit/cycle SAR ADC with Error-Tolerant Interpolation Technique

Jaegeun Song, Yunsoo Park, Chaegang Lim, Yohan Choi, Soonsung Ahn, Sooho Park, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

This article presents a 9-bit 500-MS/s 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with an error-tolerant interpolation technique. The proposed interpolation technique uses flip-flops to implement a 2-bit/cycle operation in the SAR ADC. By taking advantage of the metastable region of the flip-flop, the proposed interpolator can defer the bit decision when a decision error occurs with a high probability. Because the SAR ADC approximates the signal range step by step, the deferred decisions proceed to the next conversion cycles without any increase in quantization noise. The deferring-decision characteristic increases the error tolerance in the presence of comparator mismatches and increases the inherent linearity of the interpolation technique compared to conventional latch interpolation. A prototype ADC was designed using the 28-nm CMOS technology to verify the effectiveness of the proposed interpolation technique. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at the Nyquist rate are 50.6 and 61.4 dB, respectively. The power consumption is 1.87 mW at a sampling frequency of 500 MS/s. The proposed ADC achieves a Walden figure of merit (FoM) of 13.5 fJ/conversion-step.

Original languageEnglish
Pages (from-to)1492-1503
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume57
Issue number5
DOIs
Publication statusPublished - 2022 May 1

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

  • 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC)
  • Flip-flop
  • High-speed SAR ADC
  • Interpolation technique

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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