A 9 Gb/s/ch Transceiver with Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces

Junyoung Song; Yongtae Kim; Chulwoo Kim

doi:10.1109/TCSII.2019.2893498

A 9 Gb/s/ch Transceiver with Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces

Junyoung Song, Yongtae Kim, Chulwoo Kim

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10^-12 bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 ps_RMS. In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.

Original language	English
Article number	8628259
Pages (from-to)	1982-1986
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	66
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2019.2893498
Publication status	Published - 2019 Dec

Bibliographical note

Funding Information:
Manuscript received October 14, 2018; revised November 19, 2018; accepted January 1, 2019. Date of publication January 28, 2019; date of current version December 6, 2019. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant NRF-2018R1D1A1A02086062. This brief was recommended by Associate Editor M. H. Chowdhury. (Corresponding author: Chulwoo Kim.) J. Song is with the Department of Electronics Engineering, Incheon National University, Incheon 22012, South Korea.

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

DRAM
data-embedded clock signaling
graphics DRAM
memory interface
multi-level signaling
reference-less interface
transceiver

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2019.2893498

Cite this

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title = "A 9 Gb/s/ch Transceiver with Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces",

abstract = "A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10-12 bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 psRMS. In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.",

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author = "Junyoung Song and Yongtae Kim and Chulwoo Kim",

note = "Funding Information: Manuscript received October 14, 2018; revised November 19, 2018; accepted January 1, 2019. Date of publication January 28, 2019; date of current version December 6, 2019. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant NRF-2018R1D1A1A02086062. This brief was recommended by Associate Editor M. H. Chowdhury. (Corresponding author: Chulwoo Kim.) J. Song is with the Department of Electronics Engineering, Incheon National University, Incheon 22012, South Korea. Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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AB - A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10-12 bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 psRMS. In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.

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A 9 Gb/s/ch Transceiver with Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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