TY - JOUR
T1 - A 9 Gb/s/ch Transceiver with Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces
AU - Song, Junyoung
AU - Kim, Yongtae
AU - Kim, Chulwoo
N1 - Funding Information:
Manuscript received October 14, 2018; revised November 19, 2018; accepted January 1, 2019. Date of publication January 28, 2019; date of current version December 6, 2019. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant NRF-2018R1D1A1A02086062. This brief was recommended by Associate Editor M. H. Chowdhury. (Corresponding author: Chulwoo Kim.) J. Song is with the Department of Electronics Engineering, Incheon National University, Incheon 22012, South Korea.
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10-12 bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 psRMS. In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.
AB - A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10-12 bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 psRMS. In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.
KW - DRAM
KW - data-embedded clock signaling
KW - graphics DRAM
KW - memory interface
KW - multi-level signaling
KW - reference-less interface
KW - transceiver
UR - http://www.scopus.com/inward/record.url?scp=85076988169&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2019.2893498
DO - 10.1109/TCSII.2019.2893498
M3 - Article
AN - SCOPUS:85076988169
SN - 1549-7747
VL - 66
SP - 1982
EP - 1986
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 12
M1 - 8628259
ER -