A Capacitively Coupled CT Δ Σm with Chopping Artifacts Rejection for Sensor Readout ICs

Chaegang Lim; Yohan Choi; Yunsoo Park; Jaegeun Song; Soon Sung Ahn; Sooho Park; Chulwoo Kim

doi:10.1109/TCSI.2021.3084350

A Capacitively Coupled CT Δ Σm with Chopping Artifacts Rejection for Sensor Readout ICs

Chaegang Lim, Yohan Choi, Yunsoo Park, Jaegeun Song, Soon Sung Ahn, Sooho Park, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time Δ Σ modulator (CT Δ Σ M ) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( fch ) same as the sampling frequency ( fs ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT Δ Σ M. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT Δ Σ M has a 19.4 nV Hz input-referred noise density, 1.9μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV pp. With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

Original language	English
Article number	9446071
Pages (from-to)	3242-3253
Number of pages	12
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	68
Issue number	8
DOIs	https://doi.org/10.1109/TCSI.2021.3084350
Publication status	Published - 2021 Aug

Bibliographical note

Funding Information:
Manuscript received February 8, 2021; revised April 26, 2021; accepted May 12, 2021. Date of publication June 3, 2021; date of current version July 13, 2021. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) under Grant 2019R1A2B5B03100756. This article was recommended by Associate Editor Shuang Zhu. (Chaegang Lim and Yohan Choi contributed equally to this work.) (Corresponding author: Chulwoo Kim.) The authors are with the Department of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: [email protected]).

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

1/ f noise
CCIA
CTδσM
RRL
analog-to-digital converter (ADC)
chopping artifacts
chopping technique
noisefolding
ripple
sensor readout IC
spike

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TCSI.2021.3084350

Cite this

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title = "A Capacitively Coupled CT Δ Σm with Chopping Artifacts Rejection for Sensor Readout ICs",

abstract = "This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time Δ Σ modulator (CT Δ Σ M ) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( fch ) same as the sampling frequency ( fs ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT Δ Σ M. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT Δ Σ M has a 19.4 nV Hz input-referred noise density, 1.9μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV pp. With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. ",

keywords = "1/ f noise, CCIA, CTδσM, RRL, analog-to-digital converter (ADC), chopping artifacts, chopping technique, noisefolding, ripple, sensor readout IC, spike",

author = "Chaegang Lim and Yohan Choi and Yunsoo Park and Jaegeun Song and Ahn, {Soon Sung} and Sooho Park and Chulwoo Kim",

note = "Funding Information: Manuscript received February 8, 2021; revised April 26, 2021; accepted May 12, 2021. Date of publication June 3, 2021; date of current version July 13, 2021. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) under Grant 2019R1A2B5B03100756. This article was recommended by Associate Editor Shuang Zhu. (Chaegang Lim and Yohan Choi contributed equally to this work.) (Corresponding author: Chulwoo Kim.) The authors are with the Department of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: [email protected]). Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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AU - Lim, Chaegang

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AU - Song, Jaegeun

AU - Ahn, Soon Sung

AU - Park, Sooho

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received February 8, 2021; revised April 26, 2021; accepted May 12, 2021. Date of publication June 3, 2021; date of current version July 13, 2021. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) under Grant 2019R1A2B5B03100756. This article was recommended by Associate Editor Shuang Zhu. (Chaegang Lim and Yohan Choi contributed equally to this work.) (Corresponding author: Chulwoo Kim.) The authors are with the Department of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: [email protected]). Publisher Copyright: © 2004-2012 IEEE.

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N2 - This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time Δ Σ modulator (CT Δ Σ M ) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( fch ) same as the sampling frequency ( fs ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT Δ Σ M. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT Δ Σ M has a 19.4 nV Hz input-referred noise density, 1.9μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV pp. With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

AB - This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time Δ Σ modulator (CT Δ Σ M ) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( fch ) same as the sampling frequency ( fs ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT Δ Σ M. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT Δ Σ M has a 19.4 nV Hz input-referred noise density, 1.9μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV pp. With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

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A Capacitively Coupled CT Δ Σm with Chopping Artifacts Rejection for Sensor Readout ICs

Abstract

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Keywords

ASJC Scopus subject areas

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