Abstract
Recently, single-ISA heterogemeous multi-core processors (SI- HMP) draw attention, pursuing optimal power-performance scaling. Leveraging differently optimized heterogeneous cores, SI-HMP can dynamically tune performance with minimal additional power consumption, or it can find maximum per- formance core combination with respect to a given power budget. However, the little-to-big, or big-to-little core switch- ing has hidden costs. To properly scale up/down the power- performance, we should carefully analyze the actual perfor- mance gain, considering the multi-core processing model and inter-cluster communication. This paper reveals that there are some good and bad cases for core switching, and presents a possible way to achieve good power-performance scaling through big-little switching.
| Original language | English |
|---|---|
| Title of host publication | 2015 Workshop on Power-Aware Computing and Systems, HotPower 2015 |
| Publisher | Association for Computing Machinery, Inc |
| Pages | 1-5 |
| Number of pages | 5 |
| ISBN (Electronic) | 9781450339469 |
| DOIs | |
| Publication status | Published - 2015 Oct 4 |
| Externally published | Yes |
| Event | 2015 Workshop on Power-Aware Computing and Systems, HotPower 2015 - Monterey, United States Duration: 2015 Oct 4 → … |
Publication series
| Name | 2015 Workshop on Power-Aware Computing and Systems, HotPower 2015 |
|---|
Conference
| Conference | 2015 Workshop on Power-Aware Computing and Systems, HotPower 2015 |
|---|---|
| Country/Territory | United States |
| City | Monterey |
| Period | 15/10/4 → … |
Bibliographical note
Publisher Copyright:© 2015 ACM.
Keywords
- Power- per- formance
- Single-ISA heterogeneous multi-core architecture
ASJC Scopus subject areas
- Software
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