A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference

Joonhyung Kim; Jongsun Park

doi:10.1109/ISOCC53507.2021.9613938

A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference

Joonhyung Kim, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

SRAM-based In-Memory-Computing (IMC) for processing multiply-Accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	89-90
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613938
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Funding Information:
This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820).

Publisher Copyright:
© 2021 IEEE.

Keywords

Deep Neural Network (DNN)
In-Memory Computing(IMC)
Multiply-Accumulate (MAC)
SRAM

ASJC Scopus subject areas

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613938

Cite this

Kim, J., & Park, J. (2021). A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 89-90). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613938

A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference. / Kim, Joonhyung; Park, Jongsun.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 89-90 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, J & Park, J 2021, A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 89-90, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613938

Kim J, Park J. A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference. In Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 89-90. (Proceedings - International SoC Design Conference 2021, ISOCC 2021). doi: 10.1109/ISOCC53507.2021.9613938

@inproceedings{3a72c935192a4027b83eddb169c6defb,

title = "A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference",

abstract = "SRAM-based In-Memory-Computing (IMC) for processing multiply-Accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.",

keywords = "Deep Neural Network (DNN), In-Memory Computing(IMC), Multiply-Accumulate (MAC), SRAM",

author = "Joonhyung Kim and Jongsun Park",

note = "Funding Information: This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820). Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613938",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "89--90",

booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

}

TY - GEN

T1 - A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference

AU - Kim, Joonhyung

AU - Park, Jongsun

PY - 2021

Y1 - 2021

N2 - SRAM-based In-Memory-Computing (IMC) for processing multiply-Accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.

AB - SRAM-based In-Memory-Computing (IMC) for processing multiply-Accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.

KW - Deep Neural Network (DNN)

KW - In-Memory Computing(IMC)

KW - Multiply-Accumulate (MAC)

KW - SRAM

UR - http://www.scopus.com/inward/record.url?scp=85123385225&partnerID=8YFLogxK

U2 - 10.1109/ISOCC53507.2021.9613938

DO - 10.1109/ISOCC53507.2021.9613938

M3 - Conference contribution

AN - SCOPUS:85123385225

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 89

EP - 90

BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International System-on-Chip Design Conference, ISOCC 2021

Y2 - 6 October 2021 through 9 October 2021

ER -

A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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