TY - GEN
T1 - A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference
AU - Kim, Joonhyung
AU - Park, Jongsun
N1 - Funding Information:
This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820).
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - SRAM-based In-Memory-Computing (IMC) for processing multiply-Accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.
AB - SRAM-based In-Memory-Computing (IMC) for processing multiply-Accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.
KW - Deep Neural Network (DNN)
KW - In-Memory Computing(IMC)
KW - Multiply-Accumulate (MAC)
KW - SRAM
UR - http://www.scopus.com/inward/record.url?scp=85123385225&partnerID=8YFLogxK
U2 - 10.1109/ISOCC53507.2021.9613938
DO - 10.1109/ISOCC53507.2021.9613938
M3 - Conference contribution
AN - SCOPUS:85123385225
T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021
SP - 89
EP - 90
BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th International System-on-Chip Design Conference, ISOCC 2021
Y2 - 6 October 2021 through 9 October 2021
ER -