SRAM-based In-Memory-Computing (IMC) for processing multiply-Accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.
|Title of host publication||Proceedings - International SoC Design Conference 2021, ISOCC 2021|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2021|
|Event||18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of|
Duration: 2021 Oct 6 → 2021 Oct 9
|Name||Proceedings - International SoC Design Conference 2021, ISOCC 2021|
|Conference||18th International System-on-Chip Design Conference, ISOCC 2021|
|Country/Territory||Korea, Republic of|
|Period||21/10/6 → 21/10/9|
Bibliographical noteFunding Information:
This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820).
© 2021 IEEE.
- Deep Neural Network (DNN)
- In-Memory Computing(IMC)
- Multiply-Accumulate (MAC)
ASJC Scopus subject areas
- Computer Networks and Communications
- Information Systems
- Hardware and Architecture
- Electrical and Electronic Engineering