A charge-recycling assist technique for reliable and low power SRAM Design

Woong Choi; Jongsun Park

doi:10.1109/TCSI.2016.2589118

A charge-recycling assist technique for reliable and low power SRAM Design

Woong Choi, Jongsun Park

Research output: Contribution to journal › Article › peer-review

20 Citations (Scopus)

Abstract

This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the dynamic power consumption at ISO minimum operating voltage (MIN) condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit.

Original language	English
Article number	7524740
Pages (from-to)	1164-1175
Number of pages	12
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	63
Issue number	8
DOIs	https://doi.org/10.1109/TCSI.2016.2589118
Publication status	Published - 2016 Aug

Bibliographical note

Funding Information:
This work was supported by the Information Technology Research and Development Program of Korea Evaluation Institute of Industrial Technology (KEIT) [10052716, Design technology development of ultralow voltage operating circuit and IP for smart sensor SoC]. This work was also supported by National Research Foundation of Korea (#2015M3D1A1070465).

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

Assist
SRAM
capacitive coupling
charge-recycling
read stability
variation
write ability

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSI.2016.2589118

Cite this

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abstract = "This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the dynamic power consumption at ISO minimum operating voltage (MIN) condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit.",

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A charge-recycling assist technique for reliable and low power SRAM Design

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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