Abstract
This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the dynamic power consumption at ISO minimum operating voltage (MIN) condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit.
Original language | English |
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Article number | 7524740 |
Pages (from-to) | 1164-1175 |
Number of pages | 12 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 63 |
Issue number | 8 |
DOIs | |
Publication status | Published - 2016 Aug |
Keywords
- Assist
- SRAM
- capacitive coupling
- charge-recycling
- read stability
- variation
- write ability
ASJC Scopus subject areas
- Electrical and Electronic Engineering