A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling

Jin Han Kim; Young Ho Kwak; Seok Ryung Yoon; Moo Young Kim; Soo Won Kim; Chulwoo Kim

A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling

Jin Han Kim, Young Ho Kwak, Seok Ryung Yoon, Moo Young Kim, Soo Won Kim, Chulwoo Kim

Research output: Contribution to journal › Conference article › peer-review

Abstract

A DLL-based clock generator for dynamic frequency scaling is fabricated in a 0.35μm CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The frequency can be dynamically changed. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of ±6.6ps_pp at 1.3GHz.

Original language	English
Article number	28.4
Pages (from-to)	428-429+718
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	48
Publication status	Published - 2005
Event	2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2005 Feb 6 → 2005 Feb 10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling",

abstract = "A DLL-based clock generator for dynamic frequency scaling is fabricated in a 0.35μm CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The frequency can be dynamically changed. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of ±6.6pspp at 1.3GHz.",

author = "Kim, {Jin Han} and Kwak, {Young Ho} and Yoon, {Seok Ryung} and Kim, {Moo Young} and Kim, {Soo Won} and Chulwoo Kim",

year = "2005",

language = "English",

volume = "48",

pages = "428--429+718",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2005 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2005 Through 10-02-2005",

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T1 - A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling

AU - Kim, Jin Han

AU - Kwak, Young Ho

AU - Yoon, Seok Ryung

AU - Kim, Moo Young

AU - Kim, Soo Won

AU - Kim, Chulwoo

PY - 2005

Y1 - 2005

N2 - A DLL-based clock generator for dynamic frequency scaling is fabricated in a 0.35μm CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The frequency can be dynamically changed. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of ±6.6pspp at 1.3GHz.

AB - A DLL-based clock generator for dynamic frequency scaling is fabricated in a 0.35μm CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The frequency can be dynamically changed. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of ±6.6pspp at 1.3GHz.

UR - http://www.scopus.com/inward/record.url?scp=28144464493&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:28144464493

SN - 0193-6530

VL - 48

SP - 428-429+718

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

M1 - 28.4

T2 - 2005 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2005 through 10 February 2005

ER -

A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling

Abstract

ASJC Scopus subject areas

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