TY - GEN
T1 - A CMOS readout IC design for uncooled infrared bolometer image sensor application
AU - Hwang, Sang Joon
AU - Shin, Aram
AU - Shin, Ho Hyun
AU - Sung, Man Young
PY - 2006
Y1 - 2006
N2 - As infrared light is radiated, the CMOS Readout IC (ROIC) for the microbolometer type infrared sensor detects voltage or current when the resistance value in the bolometer sensor varies. One of the serious problems in designing the ROIC is that resistances in the bolometer and replica resistor have process variation. This means that each pixel does not have the same resistance, causing serious fixed pattern noise problems in sensor operations. In this paper, differential input stage readout architecture is suggested for bias offset reduction, noise immunity and high sensing margin. In addition, using this scheme the effects of a process variation problem and various other bias heating noise problems, are reduced. In this paper, a prototype ROICs, intended for uncooled microbolometer infrared focal plane array, is designed and fabricated. The proposed architecture is demonstrated by fabrication of a prototype consisting of 32 × 32 pixels fabricated in a 0.25-μm CMOS process.
AB - As infrared light is radiated, the CMOS Readout IC (ROIC) for the microbolometer type infrared sensor detects voltage or current when the resistance value in the bolometer sensor varies. One of the serious problems in designing the ROIC is that resistances in the bolometer and replica resistor have process variation. This means that each pixel does not have the same resistance, causing serious fixed pattern noise problems in sensor operations. In this paper, differential input stage readout architecture is suggested for bias offset reduction, noise immunity and high sensing margin. In addition, using this scheme the effects of a process variation problem and various other bias heating noise problems, are reduced. In this paper, a prototype ROICs, intended for uncooled microbolometer infrared focal plane array, is designed and fabricated. The proposed architecture is demonstrated by fabrication of a prototype consisting of 32 × 32 pixels fabricated in a 0.25-μm CMOS process.
UR - http://www.scopus.com/inward/record.url?scp=43249105424&partnerID=8YFLogxK
U2 - 10.1109/ISIE.2006.296056
DO - 10.1109/ISIE.2006.296056
M3 - Conference contribution
AN - SCOPUS:43249105424
SN - 1424404975
SN - 9781424404971
T3 - IEEE International Symposium on Industrial Electronics
SP - 2788
EP - 2791
BT - International Symposium on Industrial Electronics 2006, ISIE 2006
T2 - International Symposium on Industrial Electronics 2006, ISIE 2006
Y2 - 9 July 2006 through 13 July 2006
ER -