A Compact 10b Source Driver IC with Delta-Sigma Pulse Width Modulation for Low-Voltage Digital Interpolation Achieving 1884μm²/Channel

Recently, higher display resolution of flagship smartphones has contributed to better quality 3D image rendering and mobile gaming applications. However, high-resolution displays require source-driver ICs (SD-IC) with more channels, significantly increasing the silicon area and cost. One of the effective approaches for compact channel area is utilizing the piecewise-linear interpolation method for a digial-to-analog conveter (DAC), which is required for each channel in the SD-IC [1]-[5]. Figure 6.9.1 (top) depicts the conventional interpolation sub-DAC topologies in which a resistor-string DAC (RDAC) selects two adjacent gamma voltages (VH and VL) and the sub DAC linearly divides between VH and VL. DAC-embedded amplifiers [1], [2] interpolate between VH and VL by adjusting the transconductance (Gm) of each input transistor, but the inherent nonlinearity of Gm results in interpolation errors, degrading the DAC resolution. Another interpolation methods, such as switched-capacitor (SC) sub-DACs [2]-[4] and charge-modulation (QM) DACs [5], exhibit better linearity, but the addition of capacitors or high-voltage transistor blocks increase the channel silicon area. To overcome these limitations, this paper presents a compact 10b SD-IC with low-voltage (LV) delta-sigma pulse-width-modulation (SD-PWM) interpolation DACs.