A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method

Coordinate Rotational Digital Computer (CORDIC) has been widely used as an iterative algorithm for performing rotations in many digital signal processing (DSP) applications. The CORDIC algorithm is divided into two modes, which are the rotation and vectoring modes. The conventional hardware architecture of CORDIC algorithm has two problems. First, though the computations of both modes are very similar, two separate modules are used in separate hardware architecture. Second, after computations of the whole iterations, an extra scaling operation to make a normalized output has been another computational burden. In this paper, we present a compact multi-mode CORDIC architecture, where both of the rotation and vectoring modes can be performed using a shared hardware architecture. In addition, Global-Shifting-Sum (GSS) approach which uses one adder and one barrel shifter is also proposed to efficiently eliminate the scaling operation of CORDIC. The proposed multi-mode GSS CORDIC is implemented as the iterative cross-folded architecture to minimize the area of CORDIC. The experimental results with 65nm CMOS process show 42% area reduction compared to the conventional two separate hardware architectures of CORDIC with minor degradation in accuracy.