A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor

Sunghwa Ok; Jungmoon Kim; Gilwon Yoon; Hyunho Chu; Jaegeun Oh; Seon Wook Kim; Chulwoo Kim

doi:10.1109/CICC.2008.4672144

A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor

Sunghwa Ok, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim, Chulwoo Kim

Research output: Contribution to journal › Conference article › peer-review

7 Citations (Scopus)

Abstract

This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-μm CMOS process. The implemented DVS circuit provides a supply voltage from 1.4V to 1.8V and the DFS circuit dynamically generates the system clock from 7.5MHz to 120MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm² and 0.27 mm² active areas, respectively.

Original language	English
Article number	4672144
Pages (from-to)	551-554
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672144
Publication status	Published - 2008
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: 2008 Sept 21 → 2008 Sept 24

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/CICC.2008.4672144

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title = "A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor",

abstract = "This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-μm CMOS process. The implemented DVS circuit provides a supply voltage from 1.4V to 1.8V and the DFS circuit dynamically generates the system clock from 7.5MHz to 120MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm2 and 0.27 mm2 active areas, respectively.",

author = "Sunghwa Ok and Jungmoon Kim and Gilwon Yoon and Hyunho Chu and Jaegeun Oh and Kim, {Seon Wook} and Chulwoo Kim",

year = "2008",

doi = "10.1109/CICC.2008.4672144",

language = "English",

pages = "551--554",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 ; Conference date: 21-09-2008 Through 24-09-2008",

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T1 - A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor

AU - Ok, Sunghwa

AU - Kim, Jungmoon

AU - Yoon, Gilwon

AU - Chu, Hyunho

AU - Oh, Jaegeun

AU - Kim, Seon Wook

AU - Kim, Chulwoo

PY - 2008

Y1 - 2008

N2 - This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-μm CMOS process. The implemented DVS circuit provides a supply voltage from 1.4V to 1.8V and the DFS circuit dynamically generates the system clock from 7.5MHz to 120MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm2 and 0.27 mm2 active areas, respectively.

AB - This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-μm CMOS process. The implemented DVS circuit provides a supply voltage from 1.4V to 1.8V and the DFS circuit dynamically generates the system clock from 7.5MHz to 120MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm2 and 0.27 mm2 active areas, respectively.

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A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor

Abstract

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