Abstract
Redundancy repairs are commonly used to support fault tolerance in DRAM systems and recently, the processor performance has been greatly improved, so DRAM access latency has become an important issue. However, existing redundancy repairs using shift logic have difficulty in further reducing the latency due to their design limitations. In this paper, we propose a novel, decoupled bit shifting technique that uses data encoding and decoding to resolve this limitation. Our technique decouples the conventional shifting logic into two units, a bit selection vector generator (BSVG) and a data manipulation unit (DMU), to reduce the latency overhead of the shifting logic. Our technique can apply the BSVG in parallel with other logic consuming long latency operations, thereby reducing the total latency compared to conventional shifting logic. We implement both serial and parallel approaches to demonstrate that the parallel approach performs significantly better than the serial one in terms of delay, area, and dynamic power consumption. The experimental results show that our bit shifting technique is applicable for redundancy repair technique in state-of-the-art DRAM architectures.
Original language | English |
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Article number | 20170385 |
Journal | ieice electronics express |
Volume | 14 |
Issue number | 13 |
DOIs | |
Publication status | Published - 2017 |
Bibliographical note
Funding Information:This work was supported by the IT R&D program of MOTIE/KEIT. [10052653, Development of processing in memory architecture and parallel processing for data bounding applications]
Publisher Copyright:
© IEICE 2017.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
Keywords
- Bit shifting
- DRAM
- Decoding
- Encoding
- Redundancy repair
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering