A delay line with highly linear thermal sensitivity for smart temperature sensor

Nguyen Thanh Trung; Kwansu Shon; Soo Won Kim

doi:10.1109/MWSCAS.2007.4488716

A delay line with highly linear thermal sensitivity for smart temperature sensor

Nguyen Thanh Trung, Kwansu Shon, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A highly linear thermal sensitivity delay line for smart temperature sensor is presented. The proposed delay line is a current starved inverter chain. A simple bias current source circuit is incorporated with the delay line to generate a current inversely proportional to temperature based on the transconductance characteristics of a MOS device at the vicinity of the zero temperature coefficient (ZTC) point. Simulation results in a 0.18μm CMOS technology show that the proposed delay line has a higher linearity within 0.24 °C in a wider temperature range from -40°C to 120°C compared with conventional structures.

Original language	English
Title of host publication	2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
Pages	899-902
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2007.4488716
Publication status	Published - 2007
Event	2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference - Montreal, QC, Canada Duration: 2007 Aug 5 → 2007 Aug 8

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746

Other

Other	2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
Country/Territory	Canada
City	Montreal, QC
Period	07/8/5 → 07/8/8

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2007.4488716

Cite this

A delay line with highly linear thermal sensitivity for smart temperature sensor. / Trung, Nguyen Thanh; Shon, Kwansu; Kim, Soo Won.
2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings. 2007. p. 899-902 4488716 (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Trung, NT, Shon, K & Kim, SW 2007, A delay line with highly linear thermal sensitivity for smart temperature sensor. in 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings., 4488716, Midwest Symposium on Circuits and Systems, pp. 899-902, 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference, Montreal, QC, Canada, 07/8/5. https://doi.org/10.1109/MWSCAS.2007.4488716

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abstract = "A highly linear thermal sensitivity delay line for smart temperature sensor is presented. The proposed delay line is a current starved inverter chain. A simple bias current source circuit is incorporated with the delay line to generate a current inversely proportional to temperature based on the transconductance characteristics of a MOS device at the vicinity of the zero temperature coefficient (ZTC) point. Simulation results in a 0.18μm CMOS technology show that the proposed delay line has a higher linearity within 0.24 °C in a wider temperature range from -40°C to 120°C compared with conventional structures.",

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AB - A highly linear thermal sensitivity delay line for smart temperature sensor is presented. The proposed delay line is a current starved inverter chain. A simple bias current source circuit is incorporated with the delay line to generate a current inversely proportional to temperature based on the transconductance characteristics of a MOS device at the vicinity of the zero temperature coefficient (ZTC) point. Simulation results in a 0.18μm CMOS technology show that the proposed delay line has a higher linearity within 0.24 °C in a wider temperature range from -40°C to 120°C compared with conventional structures.

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A delay line with highly linear thermal sensitivity for smart temperature sensor

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