A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2^nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.