A digital LDO regulator with a self-clocking burst logic for ultralow power applications

Seong Jin Yun; Jiseong Lee; Yun Chan Im; Yong Sin Kim

doi:10.1109/TVLSI.2019.2920910

A digital LDO regulator with a self-clocking burst logic for ultralow power applications

Seong Jin Yun, Jiseong Lee, Yun Chan Im, Yong Sin Kim

Research output: Contribution to journal › Article › peer-review

11 Citations (Scopus)

Abstract

Conventional capless digital low-dropout (DLDO) regulators adopt either a high-speed clock or the burst mode at the expense of a larger quiescent current in order to overcome the degradation of the load transient response caused by the absence of an external capacitor, which causes high power consumption. In this paper, a capless DLDO regulator with a self-clocking burst logic for ultralow power applications is proposed. The self-generated clock in the burst mode of the proposed burst logic is activated temporally in order to achieve both faster load transient response and lower quiescent current. The proposed DLDO regulator is implemented in 14-nm FinFET CMOS technology. The quiescent current and figure-of-merit (FoM) of the proposed DLDO regulator are 0.69 μA and 0.097 ps, respectively, with an active area of 0.0035 mm², excluding a 0.1-nF integrated output capacitor.

Original language	English
Article number	8746678
Pages (from-to)	2237-2245
Number of pages	9
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	27
Issue number	10
DOIs	https://doi.org/10.1109/TVLSI.2019.2920910
Publication status	Published - 2019 Oct

Bibliographical note

Funding Information:
Manuscript received January 25, 2019; revised April 25, 2019; accepted May 21, 2019. Date of publication June 26, 2019; date of current version September 25, 2019. This work was supported in part by the Ministry of Trade, Industry & Energy (MOTIE), South Korea, through the Technology Innovation Program (Development of Multi-Source Cohesive Energy Harvesting and Ultralow-Power Consumption Self-Powered Iot Device Platform) under Grant 10073185 and in part by the Korea Electric Power Corporation (KEPCO), South Korea, through the Open Research and Development Program under Grant KEPCO-2017-11. (Corresponding author: Yong Sin Kim.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

Publisher Copyright:
© 1993-2012 IEEE.

Keywords

Burst mode
digital low-dropout (DLDO) regulator
low quiescent current
self-generated temporal clock

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2019.2920910

Cite this

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abstract = "Conventional capless digital low-dropout (DLDO) regulators adopt either a high-speed clock or the burst mode at the expense of a larger quiescent current in order to overcome the degradation of the load transient response caused by the absence of an external capacitor, which causes high power consumption. In this paper, a capless DLDO regulator with a self-clocking burst logic for ultralow power applications is proposed. The self-generated clock in the burst mode of the proposed burst logic is activated temporally in order to achieve both faster load transient response and lower quiescent current. The proposed DLDO regulator is implemented in 14-nm FinFET CMOS technology. The quiescent current and figure-of-merit (FoM) of the proposed DLDO regulator are 0.69 μA and 0.097 ps, respectively, with an active area of 0.0035 mm2, excluding a 0.1-nF integrated output capacitor.",

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note = "Funding Information: Manuscript received January 25, 2019; revised April 25, 2019; accepted May 21, 2019. Date of publication June 26, 2019; date of current version September 25, 2019. This work was supported in part by the Ministry of Trade, Industry & Energy (MOTIE), South Korea, through the Technology Innovation Program (Development of Multi-Source Cohesive Energy Harvesting and Ultralow-Power Consumption Self-Powered Iot Device Platform) under Grant 10073185 and in part by the Korea Electric Power Corporation (KEPCO), South Korea, through the Open Research and Development Program under Grant KEPCO-2017-11. (Corresponding author: Yong Sin Kim.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Publisher Copyright: {\textcopyright} 1993-2012 IEEE.",

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A digital LDO regulator with a self-clocking burst logic for ultralow power applications

Abstract

Bibliographical note

Keywords

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