Abstract
A digitally controlled phase-locked loop (DCPLL) that achieves fast acquisition by employing a digital phase-frequency detector (DPFD) and a variable loop gain scheme was developed for an advanced clock synthesizer and was fabricated in a 3.3-V 0.6-μm CMOS process. The DPFD was developed to measure the frequency difference and to generate digital outputs corresponding to the difference. Using these features, the DCPLL achieves ideally one-cycle frequency acquisition when programmed with an appropriate gain. The experimental results show that the fabricated DCPLL exhibits three-cycle and one-cycle frequency acquisitions, when locking to 400 MHz (VCO at 800 MHz) and 200 MHz (VCO at 400 MHz), respectively.
Original language | English |
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Pages (from-to) | 1574-1581 |
Number of pages | 8 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 36 |
Issue number | 10 |
DOIs | |
Publication status | Published - 2001 Oct |
ASJC Scopus subject areas
- Electrical and Electronic Engineering