TY - GEN
T1 - A DRAM based physical unclonable function capable of generating >1032 Challenge Response Pairs per 1Kbit array for secure chip authentication
AU - Tang, Qianying
AU - Zhou, Chen
AU - Choi, Woong
AU - Kang, Gyuseong
AU - Park, Jongsun
AU - Parhi, Keshab K.
AU - Kim, Chris H.
N1 - Funding Information:
This work was supported in part by the National Science Foundation under Grant CNS-1441639, and in part by the Semiconductor Research Corporation under Contract 2014-TS-2560.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/26
Y1 - 2017/7/26
N2 - A DRAM based Physical Unclonable Function (PUF) utilizing the location of weak retention cells is demonstrated in 65nm CMOS. A new authentication scheme is proposed for the DRAM PUF where a random pattern is written to a small section of the DRAM and then retention failures are induced. To further increase the number of Challenge Response Pairs (CPRs), the data pattern including retention failures is transferred to a different memory location where additional retention failures are induced. This scheme enables more than 1032 unique CRPs from a 1Kbit array. To improve the stability of the PUF response, a zero-overhead repetitive write-back technique along with bit-masking was utilized. Voltage and temperature induced instabilities were mitigated by adjusting the read reference voltage and refresh time before each authentication operation. The proposed DRAM PUF has a bit cell area of 0.68μm2.
AB - A DRAM based Physical Unclonable Function (PUF) utilizing the location of weak retention cells is demonstrated in 65nm CMOS. A new authentication scheme is proposed for the DRAM PUF where a random pattern is written to a small section of the DRAM and then retention failures are induced. To further increase the number of Challenge Response Pairs (CPRs), the data pattern including retention failures is transferred to a different memory location where additional retention failures are induced. This scheme enables more than 1032 unique CRPs from a 1Kbit array. To improve the stability of the PUF response, a zero-overhead repetitive write-back technique along with bit-masking was utilized. Voltage and temperature induced instabilities were mitigated by adjusting the read reference voltage and refresh time before each authentication operation. The proposed DRAM PUF has a bit cell area of 0.68μm2.
UR - http://www.scopus.com/inward/record.url?scp=85030458974&partnerID=8YFLogxK
U2 - 10.1109/CICC.2017.7993610
DO - 10.1109/CICC.2017.7993610
M3 - Conference contribution
AN - SCOPUS:85030458974
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 38th Annual Custom Integrated Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th Annual Custom Integrated Circuits Conference, CICC 2017
Y2 - 30 April 2017 through 3 May 2017
ER -