A Four-Phase Time-Based Switched-Capacitor LDO with 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications

Hyunjin Kim, Changhun Park, Inho Park, Taehyeong Park, Seungwoo Park, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

Abstract

This article presents a four-phase time-based switched-capacitor low-dropout (SCLDO) regulator that regulates an output load voltage (VOUT) of 0.35-0.95 V with an input voltage (VIN) of 0.45-1 V. The regulator employs a four-phase time quantizer, which enables high proportional gain control and short transient response time with relatively low quiescent current. In addition, the proposed SCLDO employs a 9.6-pF coupling capacitor (CC) that is connected to the gate voltage of the pass transistor and VOUT node, thereby reducing the VOUT voltage drop during the load transition. Because the SCLDO utilizes capacitor components when charging and discharging CC, it provides robustness to process and temperature variations even at low-VIN conditions. Therefore, the proposed time-based SCLDO achieved a VOUT settling time of 4.4 ns at VIN = 1 V and 13 ns at VIN = 0.5 V condition. Fabricated in a 28-nm CMOS process, the proposed time-based SCLDO achieves a maximum IOUT of 400 mA and a figure of merit (FoM) of 3.0 fs, with an active area of 0.021 mm2.

Original languageEnglish
Pages (from-to)551-562
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume59
Issue number2
DOIs
Publication statusPublished - 2024 Feb 1

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

  • Dynamic voltage and frequency scaling (DVFS)
  • fast transient response
  • fully integrated voltage regulator
  • low-dropout (LDO) regulator
  • power management
  • switchedcapacitor LDO (SCLDO)
  • time quantizer

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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