A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology

Se Chun Park; Seung Baek Park; Soo-Won Kim

doi:10.1109/ICCE.2015.7066538

A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology

Se Chun Park, Seung Baek Park, Soo-Won Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this study, a fully integrated Phase-locked loop (PLL) that is applicable to Universal Flash Storage (UFS) systems is presented. The fully integrated PLL is realized using a MOS capacitor as an on-chip loop filter (LF). To compensate for leakage current in the LF, a leakage current compensation scheme is presented. With the leakage compensation scheme, the peak-to-peak jitter and rms jitter are 40ps and 7.62ps, respectively. The area of the LF was reduced by around a sixteenth part compared with a metal insulator metal (MIM) capacitor.

Original language	English
Title of host publication	2015 IEEE International Conference on Consumer Electronics, ICCE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	587-588
Number of pages	2
ISBN (Print)	9781479975426
DOIs	https://doi.org/10.1109/ICCE.2015.7066538
Publication status	Published - 2015 Mar 23
Event	2015 IEEE International Conference on Consumer Electronics, ICCE 2015 - Las Vegas, United States Duration: 2015 Jan 9 → 2015 Jan 12

Other

Other	2015 IEEE International Conference on Consumer Electronics, ICCE 2015
Country/Territory	United States
City	Las Vegas
Period	15/1/9 → 15/1/12

Keywords

Fully integrated PLL
Leakage compensation
Leakage current
MOS capacitor
Phase-locked loops
UFS

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering
Industrial and Manufacturing Engineering

Access to Document

10.1109/ICCE.2015.7066538

Cite this

A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology. / Park, Se Chun; Park, Seung Baek; Kim, Soo-Won.
2015 IEEE International Conference on Consumer Electronics, ICCE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 587-588 7066538.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, SC, Park, SB & Kim, S-W 2015, A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology. in 2015 IEEE International Conference on Consumer Electronics, ICCE 2015., 7066538, Institute of Electrical and Electronics Engineers Inc., pp. 587-588, 2015 IEEE International Conference on Consumer Electronics, ICCE 2015, Las Vegas, United States, 15/1/9. https://doi.org/10.1109/ICCE.2015.7066538

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title = "A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology",

abstract = "In this study, a fully integrated Phase-locked loop (PLL) that is applicable to Universal Flash Storage (UFS) systems is presented. The fully integrated PLL is realized using a MOS capacitor as an on-chip loop filter (LF). To compensate for leakage current in the LF, a leakage current compensation scheme is presented. With the leakage compensation scheme, the peak-to-peak jitter and rms jitter are 40ps and 7.62ps, respectively. The area of the LF was reduced by around a sixteenth part compared with a metal insulator metal (MIM) capacitor.",

keywords = "Fully integrated PLL, Leakage compensation, Leakage current, MOS capacitor, Phase-locked loops, UFS",

author = "Park, {Se Chun} and Park, {Seung Baek} and Soo-Won Kim",

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doi = "10.1109/ICCE.2015.7066538",

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N2 - In this study, a fully integrated Phase-locked loop (PLL) that is applicable to Universal Flash Storage (UFS) systems is presented. The fully integrated PLL is realized using a MOS capacitor as an on-chip loop filter (LF). To compensate for leakage current in the LF, a leakage current compensation scheme is presented. With the leakage compensation scheme, the peak-to-peak jitter and rms jitter are 40ps and 7.62ps, respectively. The area of the LF was reduced by around a sixteenth part compared with a metal insulator metal (MIM) capacitor.

AB - In this study, a fully integrated Phase-locked loop (PLL) that is applicable to Universal Flash Storage (UFS) systems is presented. The fully integrated PLL is realized using a MOS capacitor as an on-chip loop filter (LF). To compensate for leakage current in the LF, a leakage current compensation scheme is presented. With the leakage compensation scheme, the peak-to-peak jitter and rms jitter are 40ps and 7.62ps, respectively. The area of the LF was reduced by around a sixteenth part compared with a metal insulator metal (MIM) capacitor.

KW - Fully integrated PLL

KW - Leakage compensation

KW - Leakage current

KW - MOS capacitor

KW - Phase-locked loops

KW - UFS

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BT - 2015 IEEE International Conference on Consumer Electronics, ICCE 2015

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A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology

Abstract

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Keywords

ASJC Scopus subject areas

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