A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time

Young Ho Kwak, Inhwa Jung, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)


This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

Original languageEnglish
Article number5420307
Pages (from-to)120-125
Number of pages6
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number2
Publication statusPublished - 2010 Feb

Bibliographical note

Funding Information:
Manuscript received July 24, 2009; revised October 27, 2009. Current version published February 26, 2010. This work was supported in part by Hynix Semiconductor Inc. and in part by the Korea Science and Engineering Foundation Grant R0A-2007-000-20059-0 funded by the Korea government (Ministry of Education, Science and Technology). The chip was fabricated through the MPW of IC Design Education Center (IDEC) supported by the Korea Ministry of Knowledge Economy (MKE). This paper was recommended by Associate Editor P. K. Hanumolu.


  • Electromagnetic interference (EMI)
  • Fast compensation
  • Low power
  • Process, voltage, and temperature (PVT) variation detection
  • Slew rate

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time'. Together they form a unique fingerprint.

Cite this