A hardware implementation of artificial neural networks using field programmable gate arrays

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20 Citations (Scopus)


An artificial neural network algorithm is implemented using a low-cost field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time. In this work, the training of the network is performed in the off-line computing environment and the results of the training are configured to the hardware in order to minimize the latency of the neural computation. With five 8-bit input patterns, six hidden nodes, and one 8-bit output, the implemented hardware neural network makes decisions on a set of input patterns in 11 clock cycles, or less than 200 ns with a 60 MHz clock. The result from the hardware neural computation is well predictable based on the off-line computation. This implementation may be used in level 1 hardware triggers in high energy physics experiments.

Original languageEnglish
Pages (from-to)816-820
Number of pages5
JournalNuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Issue number3
Publication statusPublished - 2007 Nov 1

Bibliographical note

Funding Information:
This work was supported by Grant no. R01-2005-000-10089-0 from the Basic Research Program of the Korea Science & Engineering Foundation and by a Korea University Grant. The author recognizes one of reviewer's extra effort to improve the readability of this manuscript significantly.


  • Artificial neural network
  • FPGA
  • Level 1 trigger
  • VHDL

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Instrumentation


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