Abstract
In the semiconductor manufacturing processes, a wafer bin map (WBM) represents electrical test results. In WBMs, defective dies often form specific local patterns; such patterns are usually caused by failure from specific processes or equipment. Thus, identifying the local patterns is crucial for finding the processes or equipment responsible for the fault. Various statistical and machine learning methods have been developed for WBM classification; however, most of the existing studies considered single WBMs. This study proposes an explainable neural network for multiple WBMs classification, named a hierarchical spatial-test attention network. Our method has a hierarchical structure that reflects the characteristics of multiple WBMs. The method has two levels of attention mechanisms to the spatial and test levels, allowing the model to attend to more and less important parts when classifying WBMs. Furthermore, we propose a spatial attention probability conveyance mechanism and test-level attention entropy penalty to improve the classification performance and interpretability of the proposed method. We applied our method on a real-world multiple WBMs dataset to demonstrate the usefulness and applicability of our method. The results confirmed that the proposed method could accurately classify defect patterns while correctly identifying defect patterns' test and location.
Original language | English |
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Pages (from-to) | 78-86 |
Number of pages | 9 |
Journal | IEEE Transactions on Semiconductor Manufacturing |
Volume | 35 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2022 Feb 1 |
Keywords
- Multiple wafer bin maps classification
- attention mechanism
- deep learning
- explainable neural network
- semiconductor manufacturing
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Industrial and Manufacturing Engineering