A High-Efficiency E-Band Power Amplifier With Optimized Output Matching Network in a 28-nm Bulk CMOS

Gunwoo Park, Seungwon Park, Sanggeun Jeon

Research output: Contribution to journalArticlepeer-review


This brief presents an E-band high-efficiency power amplifier (PA) implemented in a 28-nm bulk CMOS technology. The output matching network (OMN) is optimized for high power and high efficiency through a co-optimization technique where the optimum load admittance (Yopt) is derived by incorporating the loss of the OMN with the active device performance. In the mm-wave band, a transformer with a single turn ratio is widely used for OMN but poses a limitation on the maximum achievable conductance (Gout.max) to be seen by the output transistor. Therefore, a shunt capacitor (CL) is employed in this brief to boost ${\mathrm{ G}}_{\mathrm{ out.max}}$ up to the value required for reaching Yopt. Finally, the transformer dimension and ${\mathrm{ C}}_{\mathrm{ L}}$ are optimized for high efficiency and power through the co-optimization technique. The measurement shows that the PA exhibits more than 13.4 dBm of saturated power from 65 to 80 GHz. A peak power-added efficiency (PAE) of 27% is achieved at 71 GHz, which is the highest PAE among the reported E-band CMOS PAs to the best of authors' knowledge. The PAE is maintained higher than 20% from 65 to 75 GHz. The PA exhibits a rms EVM of -25.8 dB, average PAE of 8.7%, and average output power of 5.8 dBm with a 3-Gbps 64-QAM signal.

Original languageEnglish
Pages (from-to)1032-1036
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number3
Publication statusPublished - 2024 Mar 1

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.


  • Co-optimization
  • E-band
  • high efficiency
  • optimum output admittance
  • output matching network
  • power amplifier
  • power-added efficiency

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'A High-Efficiency E-Band Power Amplifier With Optimized Output Matching Network in a 28-nm Bulk CMOS'. Together they form a unique fingerprint.

Cite this