A high-performance processing-in-memory accelerator for inline data deduplication

Young Seo Lee, Kyung Min Kim, Ji Heon Lee, Jeong Hwan Choi, Sung Woo Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In data centers, inline data deduplication which eliminates redundant data on the fly, is crucial to significantly reduce storage cost. However, it causes substantial performance and energy overhead due to a large number of memory accesses in the conventional GPU. In this paper, we propose a highperformance processing-in-memory accelerator for inline data deduplication, called Deduplication Unit (DU) to reduce the latency and power consumption. We place the DUs in a base die or core dies of a 3D stacked memory to improve performance. Our simulation results show that the DUs in the base die reduce the latency and processing unit power consumption by 17.3% and 45.5%, on average, respectively, compared to the conventional GPU. In addition, in our thermal simulation, peak temperature of the DU is still lower than the threshold temperature.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages515-523
Number of pages9
ISBN (Electronic)9781538666487
DOIs
Publication statusPublished - 2019 Nov
Event37th IEEE International Conference on Computer Design, ICCD 2019 - Abu Dhabi, United Arab Emirates
Duration: 2019 Nov 172019 Nov 20

Publication series

NameProceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

Conference

Conference37th IEEE International Conference on Computer Design, ICCD 2019
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period19/11/1719/11/20

Keywords

  • 3D stacked memory
  • Accelerator
  • Inline data deduplication
  • Processing in memory

ASJC Scopus subject areas

  • Information Systems and Management
  • Computer Networks and Communications
  • Control and Optimization
  • Hardware and Architecture

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