A high speed low-power accumulator for direct digital frequency synthesizer

Yong Sin Kim; Sung Mo Kang

doi:10.1109/MWSYM.2006.249620

A high speed low-power accumulator for direct digital frequency synthesizer

Yong Sin Kim, Sung Mo Kang

Research output: Contribution to journal › Conference article › peer-review

10 Citations (Scopus)

Abstract

A high speed low-power 32-bit accumulator for direct digital frequency synthesizer (DDFS) is presented. The DDFS consists of a phase accumulator, a phase-to-sine amplitude converter, and a D/A converter. For accumulator design, high speed pipelining scheme is commonly used to increase throughput and to reduce power consumption. Our design decreases power consumption and the number of registers down to 24% and 37% of the conventional pipelined accumulator.

Original language	English
Article number	4014944
Pages (from-to)	502-505
Number of pages	4
Journal	IEEE MTT-S International Microwave Symposium Digest
DOIs	https://doi.org/10.1109/MWSYM.2006.249620
Publication status	Published - 2006
Externally published	Yes
Event	2006 IEEE MTT-S International Microwave Symposium Digest - San Francisco, CA, United States Duration: 2006 Jun 11 → 2006 Jun 16

Keywords

Accumulator
Direct digital frequency synthesizer (DDFS)
Gated clock
Low power
Pipelining

ASJC Scopus subject areas

Radiation
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/MWSYM.2006.249620

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abstract = "A high speed low-power 32-bit accumulator for direct digital frequency synthesizer (DDFS) is presented. The DDFS consists of a phase accumulator, a phase-to-sine amplitude converter, and a D/A converter. For accumulator design, high speed pipelining scheme is commonly used to increase throughput and to reduce power consumption. Our design decreases power consumption and the number of registers down to 24% and 37% of the conventional pipelined accumulator.",

keywords = "Accumulator, Direct digital frequency synthesizer (DDFS), Gated clock, Low power, Pipelining",

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AU - Kang, Sung Mo

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AB - A high speed low-power 32-bit accumulator for direct digital frequency synthesizer (DDFS) is presented. The DDFS consists of a phase accumulator, a phase-to-sine amplitude converter, and a D/A converter. For accumulator design, high speed pipelining scheme is commonly used to increase throughput and to reduce power consumption. Our design decreases power consumption and the number of registers down to 24% and 37% of the conventional pipelined accumulator.

KW - Accumulator

KW - Direct digital frequency synthesizer (DDFS)

KW - Gated clock

KW - Low power

KW - Pipelining

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JO - IEEE MTT-S International Microwave Symposium Digest

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ER -

A high speed low-power accumulator for direct digital frequency synthesizer

Abstract

Keywords

ASJC Scopus subject areas

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