A high throughput packet-switching network with neural network controlled bypass queueing and multiplexing

Young Keun Park; Kyung Ho Lee

doi:10.1109/ICPP.1994.31

A high throughput packet-switching network with neural network controlled bypass queueing and multiplexing

Young Keun Park, Kyung Ho Lee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a high throughput packet switching network with bypass queues based on a MIN. We improve the switch throughput by partitioning the input buffers into disjoint buffer sets and multiplexing several sets of nonblocking packets within a time slot. A neural network model is presented as a controller for packet scheduling and multiplexing in the switch.

Original language	English
Title of host publication	Proceedings of the International Conference on Parallel Processing
Publisher	Institute of Electrical and Electronics Engineers Inc.
Volume	1
ISBN (Print)	0849324939, 9780849324932
DOIs	https://doi.org/10.1109/ICPP.1994.31
Publication status	Published - 1994
Externally published	Yes
Event	23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States Duration: 1994 Aug 15 → 1994 Aug 19

Other

Other	23rd International Conference on Parallel Processing, ICPP 1994
Country/Territory	United States
City	Raleigh, NC
Period	94/8/15 → 94/8/19

ASJC Scopus subject areas

Software
General Mathematics
Hardware and Architecture

Access to Document

10.1109/ICPP.1994.31

Cite this

A high throughput packet-switching network with neural network controlled bypass queueing and multiplexing. / Park, Young Keun; Lee, Kyung Ho.
Proceedings of the International Conference on Parallel Processing. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1994. 4115683.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, YK & Lee, KH 1994, A high throughput packet-switching network with neural network controlled bypass queueing and multiplexing. in Proceedings of the International Conference on Parallel Processing. vol. 1, 4115683, Institute of Electrical and Electronics Engineers Inc., 23rd International Conference on Parallel Processing, ICPP 1994, Raleigh, NC, United States, 94/8/15. https://doi.org/10.1109/ICPP.1994.31

@inproceedings{b9037d3450224e9abfbaff1936be59ae,

title = "A high throughput packet-switching network with neural network controlled bypass queueing and multiplexing",

abstract = "This paper proposes a high throughput packet switching network with bypass queues based on a MIN. We improve the switch throughput by partitioning the input buffers into disjoint buffer sets and multiplexing several sets of nonblocking packets within a time slot. A neural network model is presented as a controller for packet scheduling and multiplexing in the switch.",

author = "Park, {Young Keun} and Lee, {Kyung Ho}",

year = "1994",

doi = "10.1109/ICPP.1994.31",

language = "English",

isbn = "0849324939",

volume = "1",

booktitle = "Proceedings of the International Conference on Parallel Processing",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "23rd International Conference on Parallel Processing, ICPP 1994 ; Conference date: 15-08-1994 Through 19-08-1994",

}

TY - GEN

T1 - A high throughput packet-switching network with neural network controlled bypass queueing and multiplexing

AU - Park, Young Keun

AU - Lee, Kyung Ho

PY - 1994

Y1 - 1994

N2 - This paper proposes a high throughput packet switching network with bypass queues based on a MIN. We improve the switch throughput by partitioning the input buffers into disjoint buffer sets and multiplexing several sets of nonblocking packets within a time slot. A neural network model is presented as a controller for packet scheduling and multiplexing in the switch.

AB - This paper proposes a high throughput packet switching network with bypass queues based on a MIN. We improve the switch throughput by partitioning the input buffers into disjoint buffer sets and multiplexing several sets of nonblocking packets within a time slot. A neural network model is presented as a controller for packet scheduling and multiplexing in the switch.

UR - http://www.scopus.com/inward/record.url?scp=84904279665&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84904279665&partnerID=8YFLogxK

U2 - 10.1109/ICPP.1994.31

DO - 10.1109/ICPP.1994.31

M3 - Conference contribution

AN - SCOPUS:84904279665

SN - 0849324939

SN - 9780849324932

VL - 1

BT - Proceedings of the International Conference on Parallel Processing

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 23rd International Conference on Parallel Processing, ICPP 1994

Y2 - 15 August 1994 through 19 August 1994

ER -

A high throughput packet-switching network with neural network controlled bypass queueing and multiplexing

Abstract

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this