Abstract
This paper proposes a high throughput packet switching network with bypass queues based on a MIN. We improve the switch throughput by partitioning the input buffers into disjoint buffer sets and multiplexing several sets of nonblocking packets within a time slot. A neural network model is presented as a controller for packet scheduling and multiplexing in the switch.
Original language | English |
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Title of host publication | Proceedings of the International Conference on Parallel Processing |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Volume | 1 |
ISBN (Print) | 0849324939, 9780849324932 |
DOIs | |
Publication status | Published - 1994 |
Externally published | Yes |
Event | 23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States Duration: 1994 Aug 15 → 1994 Aug 19 |
Other
Other | 23rd International Conference on Parallel Processing, ICPP 1994 |
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Country/Territory | United States |
City | Raleigh, NC |
Period | 94/8/15 → 94/8/19 |
ASJC Scopus subject areas
- Software
- Mathematics(all)
- Hardware and Architecture