A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

A highly reliable antifuse cell and its sensing scheme that can be actually adopted in DRAM are presented. A multi-cell structure is newly devised to circumvent the large process variation problems of the DRAM cell capacitor type antifuse system. The programming current is less than 564μA up to the nine-cell case. The experimental results show that the cumulative distribution of the successful rupture in multi-cell structure is dramatically enhanced to be less than 15% of single-cell's case and the recovery problem of the programmed cell after the thermal stress (300°C) is disappeared. In addition, also presented is a Post-Package Repair (PPR) scheme that is directly coupled to external power using additional pin for the requisite high voltage with protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1Gbit DDR SDRAM is fabricated using Samsung's advanced 50nm DRAM process technology, successfully showing the feasibility of the proposed antifuse system implemented in it.