A jitter and power analysis on DCO

Doo Chan Lee; Kyu Young Kim; Young Jae Min; Jongsun Park; Soo Won Kim

doi:10.1109/TCSII.2011.2161161

A jitter and power analysis on DCO

Doo Chan Lee, Kyu Young Kim, Young Jae Min, Jongsun Park, Soo Won Kim

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DCO design time can be significantly reduced. In order to validate our proposed mathematical modeling, the DCO has been designed and fabricated using a 0.13- μm 1.2-V CMOS process. The fabricated chip presents the root-mean-square and peak-to-peak jitters of 8.9 and 70 ps, respectively, at the output frequency of 600 MHz, under the operation range of 179-656 MHz with a 2.8-ps resolution, which clearly shows that our proposed modeling is well matched with the experimental results.

Original language	English
Article number	6008632
Pages (from-to)	560-564
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	58
Issue number	9
DOIs	https://doi.org/10.1109/TCSII.2011.2161161
Publication status	Published - 2011 Sept

Bibliographical note

Funding Information:
Manuscript received January 31, 2011; revised April 18, 2011; accepted June 1, 2011. Date of current version September 14, 2011. This work was supported in part by the Nano Intellectual Property/System on Chip Promotion Group of Seoul Research and Business Development Program (10920) and in part by Hynix Semiconductor Inc. This paper was recommended by Associate Editor P.-i. Mak.

Keywords

All-digital phase-locked loop (ADPLL)
clock generator
digitally controlled oscillator (DCO)
jitter

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2011.2161161

Cite this

@article{de163fed7a7241a180b73f635350d2fa,

title = "A jitter and power analysis on DCO",

abstract = "A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DCO design time can be significantly reduced. In order to validate our proposed mathematical modeling, the DCO has been designed and fabricated using a 0.13- μm 1.2-V CMOS process. The fabricated chip presents the root-mean-square and peak-to-peak jitters of 8.9 and 70 ps, respectively, at the output frequency of 600 MHz, under the operation range of 179-656 MHz with a 2.8-ps resolution, which clearly shows that our proposed modeling is well matched with the experimental results.",

keywords = "All-digital phase-locked loop (ADPLL), clock generator, digitally controlled oscillator (DCO), jitter",

author = "Lee, {Doo Chan} and Kim, {Kyu Young} and Min, {Young Jae} and Jongsun Park and Kim, {Soo Won}",

note = "Funding Information: Manuscript received January 31, 2011; revised April 18, 2011; accepted June 1, 2011. Date of current version September 14, 2011. This work was supported in part by the Nano Intellectual Property/System on Chip Promotion Group of Seoul Research and Business Development Program (10920) and in part by Hynix Semiconductor Inc. This paper was recommended by Associate Editor P.-i. Mak.",

year = "2011",

month = sep,

doi = "10.1109/TCSII.2011.2161161",

language = "English",

volume = "58",

pages = "560--564",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - A jitter and power analysis on DCO

AU - Lee, Doo Chan

AU - Kim, Kyu Young

AU - Min, Young Jae

AU - Park, Jongsun

AU - Kim, Soo Won

N1 - Funding Information: Manuscript received January 31, 2011; revised April 18, 2011; accepted June 1, 2011. Date of current version September 14, 2011. This work was supported in part by the Nano Intellectual Property/System on Chip Promotion Group of Seoul Research and Business Development Program (10920) and in part by Hynix Semiconductor Inc. This paper was recommended by Associate Editor P.-i. Mak.

PY - 2011/9

Y1 - 2011/9

N2 - A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DCO design time can be significantly reduced. In order to validate our proposed mathematical modeling, the DCO has been designed and fabricated using a 0.13- μm 1.2-V CMOS process. The fabricated chip presents the root-mean-square and peak-to-peak jitters of 8.9 and 70 ps, respectively, at the output frequency of 600 MHz, under the operation range of 179-656 MHz with a 2.8-ps resolution, which clearly shows that our proposed modeling is well matched with the experimental results.

AB - A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DCO design time can be significantly reduced. In order to validate our proposed mathematical modeling, the DCO has been designed and fabricated using a 0.13- μm 1.2-V CMOS process. The fabricated chip presents the root-mean-square and peak-to-peak jitters of 8.9 and 70 ps, respectively, at the output frequency of 600 MHz, under the operation range of 179-656 MHz with a 2.8-ps resolution, which clearly shows that our proposed modeling is well matched with the experimental results.

KW - All-digital phase-locked loop (ADPLL)

KW - clock generator

KW - digitally controlled oscillator (DCO)

KW - jitter

UR - http://www.scopus.com/inward/record.url?scp=80052873057&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2011.2161161

DO - 10.1109/TCSII.2011.2161161

M3 - Article

AN - SCOPUS:80052873057

SN - 1549-7747

VL - 58

SP - 560

EP - 564

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 9

M1 - 6008632

ER -

A jitter and power analysis on DCO

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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