A jitter and power analysis on DCO

Doo Chan Lee, Kyu Young Kim, Young Jae Min, Jongsun Park, Soo Won Kim

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)


A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DCO design time can be significantly reduced. In order to validate our proposed mathematical modeling, the DCO has been designed and fabricated using a 0.13- μm 1.2-V CMOS process. The fabricated chip presents the root-mean-square and peak-to-peak jitters of 8.9 and 70 ps, respectively, at the output frequency of 600 MHz, under the operation range of 179-656 MHz with a 2.8-ps resolution, which clearly shows that our proposed modeling is well matched with the experimental results.

Original languageEnglish
Article number6008632
Pages (from-to)560-564
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number9
Publication statusPublished - 2011 Sept


  • All-digital phase-locked loop (ADPLL)
  • clock generator
  • digitally controlled oscillator (DCO)
  • jitter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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