Abstract
Since PCM memory has various advantages over DRAM, it is attracting attention as the next-generation memory. However, because of a few drawbacks, such as long write latency and limited write endurance, PCM cannot be used as the conventional system's main memory. This paper proposes the last-level cache (LLC) management algorithm to improve PCM's lifetime by evicting dirty blocks evenly to the PCM. As a result, we achieved 35% longer lifetime improvement without any PCM modification.
Original language | English |
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Title of host publication | 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781665435536 |
DOIs | |
Publication status | Published - 2021 Jun 27 |
Event | 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 - Jeju, Korea, Republic of Duration: 2021 Jun 27 → 2021 Jun 30 |
Publication series
Name | 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 |
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Conference
Conference | 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 |
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Country/Territory | Korea, Republic of |
City | Jeju |
Period | 21/6/27 → 21/6/30 |
Bibliographical note
Funding Information:This work was supported in part by SK Hynix Inc.
Publisher Copyright:
© 2021 IEEE.
Keywords
- LLC
- PCM
- Wear-leveling
- bit-counter
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Networks and Communications
- Hardware and Architecture
- Information Systems
- Electrical and Electronic Engineering