A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory

Won Jun Lee, Chang Hyun Kim, Seon Wook Kim

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    Since PCM memory has various advantages over DRAM, it is attracting attention as the next-generation memory. However, because of a few drawbacks, such as long write latency and limited write endurance, PCM cannot be used as the conventional system's main memory. This paper proposes the last-level cache (LLC) management algorithm to improve PCM's lifetime by evicting dirty blocks evenly to the PCM. As a result, we achieved 35% longer lifetime improvement without any PCM modification.

    Original languageEnglish
    Title of host publication2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781665435536
    DOIs
    Publication statusPublished - 2021 Jun 27
    Event36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 - Jeju, Korea, Republic of
    Duration: 2021 Jun 272021 Jun 30

    Publication series

    Name2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021

    Conference

    Conference36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
    Country/TerritoryKorea, Republic of
    CityJeju
    Period21/6/2721/6/30

    Bibliographical note

    Funding Information:
    This work was supported in part by SK Hynix Inc.

    Publisher Copyright:
    © 2021 IEEE.

    Keywords

    • LLC
    • PCM
    • Wear-leveling
    • bit-counter

    ASJC Scopus subject areas

    • Artificial Intelligence
    • Computer Networks and Communications
    • Hardware and Architecture
    • Information Systems
    • Electrical and Electronic Engineering

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