A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory

Won Jun Lee; Chang Hyun Kim; Seon Wook Kim

doi:10.1109/ITC-CSCC52171.2021.9501266

A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory

Won Jun Lee
, Chang Hyun Kim
, Seon Wook Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Since PCM memory has various advantages over DRAM, it is attracting attention as the next-generation memory. However, because of a few drawbacks, such as long write latency and limited write endurance, PCM cannot be used as the conventional system's main memory. This paper proposes the last-level cache (LLC) management algorithm to improve PCM's lifetime by evicting dirty blocks evenly to the PCM. As a result, we achieved 35% longer lifetime improvement without any PCM modification.

Original language	English
Title of host publication	2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665435536
DOIs	https://doi.org/10.1109/ITC-CSCC52171.2021.9501266
Publication status	Published - 2021 Jun 27
Event	36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 - Jeju, Korea, Republic of Duration: 2021 Jun 27 → 2021 Jun 30

Publication series

Name	2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021

Conference

Conference	36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
Country/Territory	Korea, Republic of
City	Jeju
Period	21/6/27 → 21/6/30

Bibliographical note

Funding Information:
This work was supported in part by SK Hynix Inc.

Publisher Copyright:
© 2021 IEEE.

Keywords

LLC
PCM
Wear-leveling
bit-counter

ASJC Scopus subject areas

Artificial Intelligence
Computer Networks and Communications
Hardware and Architecture
Information Systems
Electrical and Electronic Engineering

Access to Document

10.1109/ITC-CSCC52171.2021.9501266

Cite this

Lee, W. J., Kim, C. H., & Kim, S. W. (2021). A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory. In 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 Article 9501266 (2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-CSCC52171.2021.9501266

A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory. / Lee, Won Jun; Kim, Chang Hyun; Kim, Seon Wook.
2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9501266 (2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, WJ, Kim, CH & Kim, SW 2021, A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory. in 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021., 9501266, 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021, Institute of Electrical and Electronics Engineers Inc., 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021, Jeju, Korea, Republic of, 21/6/27. https://doi.org/10.1109/ITC-CSCC52171.2021.9501266

Lee WJ, Kim CH, Kim SW. A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory. In 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9501266. (2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021). doi: 10.1109/ITC-CSCC52171.2021.9501266

Lee, Won Jun ; Kim, Chang Hyun ; Kim, Seon Wook. / A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory. 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021).

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abstract = "Since PCM memory has various advantages over DRAM, it is attracting attention as the next-generation memory. However, because of a few drawbacks, such as long write latency and limited write endurance, PCM cannot be used as the conventional system's main memory. This paper proposes the last-level cache (LLC) management algorithm to improve PCM's lifetime by evicting dirty blocks evenly to the PCM. As a result, we achieved 35\% longer lifetime improvement without any PCM modification.",

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note = "Funding Information: This work was supported in part by SK Hynix Inc. Publisher Copyright: {\textcopyright} 2021 IEEE.; 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 ; Conference date: 27-06-2021 Through 30-06-2021",

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N2 - Since PCM memory has various advantages over DRAM, it is attracting attention as the next-generation memory. However, because of a few drawbacks, such as long write latency and limited write endurance, PCM cannot be used as the conventional system's main memory. This paper proposes the last-level cache (LLC) management algorithm to improve PCM's lifetime by evicting dirty blocks evenly to the PCM. As a result, we achieved 35% longer lifetime improvement without any PCM modification.

AB - Since PCM memory has various advantages over DRAM, it is attracting attention as the next-generation memory. However, because of a few drawbacks, such as long write latency and limited write endurance, PCM cannot be used as the conventional system's main memory. This paper proposes the last-level cache (LLC) management algorithm to improve PCM's lifetime by evicting dirty blocks evenly to the PCM. As a result, we achieved 35% longer lifetime improvement without any PCM modification.

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M3 - Conference contribution

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BT - 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021

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A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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