A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time

Moo Young Kim; Dongsuk Shin; Hyunsoo Chae; Sunghwa Ok; Chulwoo Kim

doi:10.1109/CICC.2007.4405754

A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time

Moo Young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A portable multiphase clock generator, independent of input duty ratio, has been developed. The proposed open-loop and full-digital architecture has a fast lock time of two clock cycles and is a simple, robust and portable IP. In addition, the complementary delay line is implemented to achieve high phase resolution at a wide frequency range. The generator has been implemented in a 0.18um CMOS process and operates at variable input frequencies ranging from 800MHz to 1.6GHz.

Original language	English
Title of host publication	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	369-372
Number of pages	4
ISBN (Electronic)	1424407869, 9781424407866
DOIs	https://doi.org/10.1109/CICC.2007.4405754
Publication status	Published - 2007
Event	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States Duration: 2007 Sept 16 → 2007 Sept 19

Publication series

Name	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Country/Territory	United States
City	San Jose
Period	07/9/16 → 07/9/19

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2007.4405754

Cite this

Kim, M. Y., Shin, D., Chae, H., Ok, S., & Kim, C. (2007). A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 369-372). Article 4405754 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405754

A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. / Kim, Moo Young; Shin, Dongsuk; Chae, Hyunsoo et al.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 369-372 4405754 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, MY, Shin, D, Chae, H, Ok, S & Kim, C 2007, A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405754, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, Institute of Electrical and Electronics Engineers Inc., pp. 369-372, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 07/9/16. https://doi.org/10.1109/CICC.2007.4405754

Kim MY, Shin D, Chae H, Ok S, Kim C. A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 369-372. 4405754. (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). doi: 10.1109/CICC.2007.4405754

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A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time

Abstract

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