A low-jitter open-loop all-digital clock generator with two-cycle lock-time

Moo Young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

11 Citations (Scopus)


A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 $\pi$ phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18- μm CMOS process and, occupies an active area of 170 μm times 120 μm. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

Original languageEnglish
Article number4801531
Pages (from-to)1461-1469
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
Publication statusPublished - 2009 Oct

Bibliographical note

Funding Information:
Manuscript received February 01, 2008; revised May 24, 2008. First published March 16, 2009; current version published September 23, 2009. This work was supported by the Korea Science and Engineering Foundation (KOSEF) under Grant R0A-2007-000-20059-0 funded by the Korea government (MOST).


  • Clock generator
  • Clock-on-demand
  • Lock time
  • PLL
  • Portable

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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