A low-latency and area-efficient gram-schmidt-based QRD Architecture for MIMO Receiver

Dongyeob Shin, Jongsun Park

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


Despite a low algorithmic complexity, Gram-Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substituting the square roots and divisions with coordinate rotation digital computer (CORDIC) operations. In the proposed architecture, when implementing the division by the results of square root, the key design point is that the rotation directions of CORDIC are shared between vectoring and rotation modes using the orthogonality of the CORDIC rotation matrix. As a result, the division operation can be performed with the assistance of square root, leading to the hardware cost reduction. The overhead of scaling factor compensation has also been reduced with pre-scaling. The proposed low complexity scheme can be implemented in the semipipelined and iterative architectures for high throughput and small area applications, respectively. Hardware implementation results with 65-nm CMOS process show that the proposed semipipelined architecture achieves 17% and 141% improvement of normalized hardware efficiency in QRD and projection operations, respectively, compared with the conventional approaches.

Original languageEnglish
Pages (from-to)2606-2616
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number8
Publication statusPublished - 2018 Aug

Bibliographical note

Funding Information:
Manuscript received September 15, 2017; revised December 13, 2017; accepted January 2, 2018. Date of publication January 30, 2018; date of current version July 3, 2018. This work was supported in part by the National Research Foundation of South Korea under Grant NRF-2016R1A2B4015329 and in part by the Information Technology Research and Development Program of the Korea Evaluation Institute of Industrial Technology (Design technology development of ultralow voltage operating circuit and IP for smart sensor SoC) under Grant 10052716. This paper was recommended by Associate Editor G. Masera. (Corresponding author: Jongsun Park.) The authors are with the School of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: shindy919@korea.ac.kr; jongsun@ korea.ac.kr).

Publisher Copyright:
© 2004-2012 IEEE.


  • Gram-Schmidt
  • MIMO
  • QR decomposition
  • energy efficiency
  • hardware efficiency

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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