A low power adaptive equalizer for PRML disk-drive read channels

This paper presents a new pipeline architecture for low-power and high-speed digital adaptive equalizer. The proposed architecture achieves enhancement in terms of speed and power consumption by sharing the input delay stage with input data multiplication and by scaling down the supply voltage. The adaptive equalizer for PRML disk-drive read channels adopting the proposed pipeline architecture is designed and fabricated with the 0.6 μm CMOS single poly triple metal process technology. The adaptive equalizer employing proposed pipeline architecture occupies 3.2 mm × 2.2 mm, achieves maximum operating frequency of 200 MHz, and dissipates 1.22 mW/MHz at 3.3 V supply voltage. Experimental results show 16% enhancement in speed and 23% less power dissipation.