A low-power architecture for maximum a posteriori decoding

Marisa López-Vallejo; Syed Aon Mujtaba; Inkyu Lee

A low-power architecture for maximum a posteriori decoding

Marisa López-Vallejo, Syed Aon Mujtaba, Inkyu Lee

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper we present a novel architecture for soft-input soft-output (SISO) Maximum a Posteriori (MAP) decoding. The architecture leverages an ASIP (Application Specific Instruction-Set Processor) structure, where the datapath has been designed to achieve high-speed performance and low power dissipation. Salient features of this architecture include: (a) delayed renormalization of the a metrics with register by-passing to reduce latency, (b) use of register files to minimize power dissipation, and (c) microprogrammed control to achieve flexibility. The resulting architecture for the SISO-MAP decoder achieves a maximum throughput of 10.9 Msymbols/second, operating at 142 MHz and dissipating 21 mW in the datapath.

Original language	English
Pages (from-to)	47-51
Number of pages	5
Journal	Conference Record of the Asilomar Conference on Signals, Systems and Computers
Volume	1
Publication status	Published - 2002
Event	The Thirty-Sixth Asilomar Conference on Signals Systems and Computers - Pacific Groove, CA, United States Duration: 2002 Nov 3 → 2002 Nov 6

ASJC Scopus subject areas

Signal Processing
Computer Networks and Communications

Cite this

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title = "A low-power architecture for maximum a posteriori decoding",

abstract = "In this paper we present a novel architecture for soft-input soft-output (SISO) Maximum a Posteriori (MAP) decoding. The architecture leverages an ASIP (Application Specific Instruction-Set Processor) structure, where the datapath has been designed to achieve high-speed performance and low power dissipation. Salient features of this architecture include: (a) delayed renormalization of the a metrics with register by-passing to reduce latency, (b) use of register files to minimize power dissipation, and (c) microprogrammed control to achieve flexibility. The resulting architecture for the SISO-MAP decoder achieves a maximum throughput of 10.9 Msymbols/second, operating at 142 MHz and dissipating 21 mW in the datapath.",

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year = "2002",

language = "English",

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note = "The Thirty-Sixth Asilomar Conference on Signals Systems and Computers ; Conference date: 03-11-2002 Through 06-11-2002",

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TY - JOUR

T1 - A low-power architecture for maximum a posteriori decoding

AU - López-Vallejo, Marisa

AU - Mujtaba, Syed Aon

AU - Lee, Inkyu

PY - 2002

Y1 - 2002

N2 - In this paper we present a novel architecture for soft-input soft-output (SISO) Maximum a Posteriori (MAP) decoding. The architecture leverages an ASIP (Application Specific Instruction-Set Processor) structure, where the datapath has been designed to achieve high-speed performance and low power dissipation. Salient features of this architecture include: (a) delayed renormalization of the a metrics with register by-passing to reduce latency, (b) use of register files to minimize power dissipation, and (c) microprogrammed control to achieve flexibility. The resulting architecture for the SISO-MAP decoder achieves a maximum throughput of 10.9 Msymbols/second, operating at 142 MHz and dissipating 21 mW in the datapath.

AB - In this paper we present a novel architecture for soft-input soft-output (SISO) Maximum a Posteriori (MAP) decoding. The architecture leverages an ASIP (Application Specific Instruction-Set Processor) structure, where the datapath has been designed to achieve high-speed performance and low power dissipation. Salient features of this architecture include: (a) delayed renormalization of the a metrics with register by-passing to reduce latency, (b) use of register files to minimize power dissipation, and (c) microprogrammed control to achieve flexibility. The resulting architecture for the SISO-MAP decoder achieves a maximum throughput of 10.9 Msymbols/second, operating at 142 MHz and dissipating 21 mW in the datapath.

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M3 - Conference article

AN - SCOPUS:0037967628

SN - 1058-6393

VL - 1

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EP - 51

JO - Conference Record of the Asilomar Conference on Signals, Systems and Computers

JF - Conference Record of the Asilomar Conference on Signals, Systems and Computers

T2 - The Thirty-Sixth Asilomar Conference on Signals Systems and Computers

Y2 - 3 November 2002 through 6 November 2002

ER -

A low-power architecture for maximum a posteriori decoding

Abstract

ASJC Scopus subject areas

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