Abstract
A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.
Original language | English |
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Pages (from-to) | 21-25 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 56 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2009 |
Bibliographical note
Funding Information:Manuscript received March 28, 2008; revised July 07, 2008. Current version published January 16, 2009. This work was supported by Korea Government (MOST) under the Korea Science and Engineering Foundation (KOSEF) Grant R0A-2007-000-20059-0 and the fabrication was supported by IDEC. This paper was recommended by Associate Editor S. Pamarti.
Keywords
- Antiharmonic lock
- Frequency multiplier
ASJC Scopus subject areas
- Electrical and Electronic Engineering