A low-power programmable DLL-based clock generator with wide-range antiharmonic lock

Jabeom Koo; Sunghwa Ok; Chulwoo Kim

doi:10.1109/TCSII.2008.2008531

A low-power programmable DLL-based clock generator with wide-range antiharmonic lock

Jabeom Koo, Sunghwa Ok, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm² and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

Original language	English
Pages (from-to)	21-25
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	56
Issue number	1
DOIs	https://doi.org/10.1109/TCSII.2008.2008531
Publication status	Published - 2009

Bibliographical note

Funding Information:
Manuscript received March 28, 2008; revised July 07, 2008. Current version published January 16, 2009. This work was supported by Korea Government (MOST) under the Korea Science and Engineering Foundation (KOSEF) Grant R0A-2007-000-20059-0 and the fabrication was supported by IDEC. This paper was recommended by Associate Editor S. Pamarti.

Keywords

Antiharmonic lock
Frequency multiplier

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2008.2008531

Cite this

@article{72667eaf2670473898dbf85dd413c405,

title = "A low-power programmable DLL-based clock generator with wide-range antiharmonic lock",

abstract = "A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.",

keywords = "Antiharmonic lock, Frequency multiplier",

author = "Jabeom Koo and Sunghwa Ok and Chulwoo Kim",

note = "Funding Information: Manuscript received March 28, 2008; revised July 07, 2008. Current version published January 16, 2009. This work was supported by Korea Government (MOST) under the Korea Science and Engineering Foundation (KOSEF) Grant R0A-2007-000-20059-0 and the fabrication was supported by IDEC. This paper was recommended by Associate Editor S. Pamarti.",

year = "2009",

doi = "10.1109/TCSII.2008.2008531",

language = "English",

volume = "56",

pages = "21--25",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - A low-power programmable DLL-based clock generator with wide-range antiharmonic lock

AU - Koo, Jabeom

AU - Ok, Sunghwa

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received March 28, 2008; revised July 07, 2008. Current version published January 16, 2009. This work was supported by Korea Government (MOST) under the Korea Science and Engineering Foundation (KOSEF) Grant R0A-2007-000-20059-0 and the fabrication was supported by IDEC. This paper was recommended by Associate Editor S. Pamarti.

PY - 2009

Y1 - 2009

N2 - A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

AB - A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

KW - Antiharmonic lock

KW - Frequency multiplier

UR - http://www.scopus.com/inward/record.url?scp=59649114991&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2008.2008531

DO - 10.1109/TCSII.2008.2008531

M3 - Article

AN - SCOPUS:59649114991

SN - 1549-7747

VL - 56

SP - 21

EP - 25

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 1

ER -

A low-power programmable DLL-based clock generator with wide-range antiharmonic lock

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this