Abstract
We present a low power reconfigurable DCT design, which achieves considerable computational complexity reduction in DCT operation with minimum image quality degradation. The approach is based on the modification of DCT bases in a bit-wise manner. Different computational complexity/image quality trade off levels are presented and a reconfigurable architecture, which can dynamically change from one trade off level to another, is also proposed. The reconfigurable DCT architecture can achieve power savings ranging from 20% to 70% for 5 different trade off levels.
Original language | English |
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Pages (from-to) | V-17-V-20 |
Journal | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
Volume | 5 |
Publication status | Published - 2004 |
Externally published | Yes |
Event | Proceedings - IEEE International Conference on Acoustics, Speech, and Signal Processing - Montreal, Que, Canada Duration: 2004 May 17 → 2004 May 21 |
ASJC Scopus subject areas
- Software
- Signal Processing
- Electrical and Electronic Engineering