A low-power reduced swing single clock flip-flop

Chulwoo Kim; Sung Mo Steve Kang

doi:10.1109/ISCAS.2001.922360

A low-power reduced swing single clock flip-flop

Chulwoo Kim, Sung Mo Steve Kang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A reduced swing single clock flip-flop (RS/sup 2/CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS/sup 2/CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	806-809
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2001.922360
Publication status	Published - 2001
Externally published	Yes
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 2001 May 6 → 2001 May 9

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	4

Other

Other	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	01/5/6 → 01/5/9

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2001.922360

Cite this

A low-power reduced swing single clock flip-flop. / Kim, Chulwoo; Kang, Sung Mo Steve.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 806-809 922360 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, C & Kang, SMS 2001, A low-power reduced swing single clock flip-flop. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922360, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 4, pp. 806-809, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 01/5/6. https://doi.org/10.1109/ISCAS.2001.922360

@inproceedings{975dbbf015a24c18ab2527c9b1815669,

title = "A low-power reduced swing single clock flip-flop",

abstract = "A reduced swing single clock flip-flop (RS/sup 2/CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS/sup 2/CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network.",

author = "Chulwoo Kim and Kang, {Sung Mo Steve}",

year = "2001",

doi = "10.1109/ISCAS.2001.922360",

language = "English",

isbn = "0780366859",

series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

pages = "806--809",

booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

}

TY - GEN

T1 - A low-power reduced swing single clock flip-flop

AU - Kim, Chulwoo

AU - Kang, Sung Mo Steve

PY - 2001

Y1 - 2001

N2 - A reduced swing single clock flip-flop (RS/sup 2/CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS/sup 2/CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network.

AB - A reduced swing single clock flip-flop (RS/sup 2/CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS/sup 2/CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network.

UR - http://www.scopus.com/inward/record.url?scp=84888044107&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84888044107&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2001.922360

DO - 10.1109/ISCAS.2001.922360

M3 - Conference contribution

AN - SCOPUS:84888044107

SN - 0780366859

SN - 9780780366855

T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

SP - 806

EP - 809

BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001

Y2 - 6 May 2001 through 9 May 2001

ER -

A low-power reduced swing single clock flip-flop

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this