A low-power reduced swing single clock flip-flop

C. Kim, S. M. Kang

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)


A reduced swing single clock flip-flop (RS2CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS2CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network.

Original languageEnglish
Pages (from-to)IV806-IV809
JournalMaterials Research Society Symposium - Proceedings
Publication statusPublished - 2001
Externally publishedYes
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering


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