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A low-power reduced swing single clock flip-flop
C. Kim
, S. M. Kang
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Keyphrases
Flip-flop
100%
Low Power
100%
Single Clock
100%
Power Saving
66%
Internal Nodes
33%
Energy Consumption Reduction
33%
Overall Power
33%
Clock Network
33%
Engineering
Flip Flop Circuits
100%
Internal Node
33%
Reduce Power Consumption
33%