A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors

Gil Su Kim; Chulwoo Kim; Soo Won Kim

doi:10.1109/ASSCC.2007.4425692

A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors

Gil Su Kim^*, Chulwoo Kim, Soo Won Kim

^*Corresponding author for this work

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 60MHz to 1.8GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-μm CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1dBc, rms jitter of 1.497ps and peak-to-peak jitter of 11.6ps with maximum power consumption of 14.4mW at 1.8V supply.

Original language	English
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Publisher	IEEE Computer Society
Pages	308-311
Number of pages	4
ISBN (Print)	1424413605, 9781424413607
DOIs	https://doi.org/10.1109/ASSCC.2007.4425692
Publication status	Published - 2007
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: 2007 Nov 12 → 2007 Nov 14

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/Territory	Korea, Republic of
City	Jeju
Period	07/11/12 → 07/11/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2007.4425692

Cite this

A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors. / Kim, Gil Su; Kim, Chulwoo; Kim, Soo Won.
2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. IEEE Computer Society, 2007. p. 308-311 4425692 (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, GS, Kim, C & Kim, SW 2007, A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425692, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, IEEE Computer Society, pp. 308-311, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 07/11/12. https://doi.org/10.1109/ASSCC.2007.4425692

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abstract = "A 60MHz to 1.8GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-μm CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1dBc, rms jitter of 1.497ps and peak-to-peak jitter of 11.6ps with maximum power consumption of 14.4mW at 1.8V supply.",

author = "Kim, \{Gil Su\} and Chulwoo Kim and Kim, \{Soo Won\}",

year = "2007",

doi = "10.1109/ASSCC.2007.4425692",

language = "English",

isbn = "1424413605",

series = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

publisher = "IEEE Computer Society",

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N2 - A 60MHz to 1.8GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-μm CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1dBc, rms jitter of 1.497ps and peak-to-peak jitter of 11.6ps with maximum power consumption of 14.4mW at 1.8V supply.

AB - A 60MHz to 1.8GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-μm CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1dBc, rms jitter of 1.497ps and peak-to-peak jitter of 11.6ps with maximum power consumption of 14.4mW at 1.8V supply.

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M3 - Conference contribution

AN - SCOPUS:51349102548

SN - 1424413605

SN - 9781424413607

T3 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

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BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

PB - IEEE Computer Society

T2 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Y2 - 12 November 2007 through 14 November 2007

ER -

A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors

Abstract

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Other

ASJC Scopus subject areas

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