A low-swing clock double-edge triggered flip-flop

Chulwoo Kim, Sung Mo Kang

Research output: Contribution to journalArticlepeer-review

72 Citations (Scopus)


A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V t transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network.

Original languageEnglish
Pages (from-to)648-652
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Issue number5
Publication statusPublished - 2002 May
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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