A low-swing clock double-edge triggered flip-flop

C. Kim; S. M. Kang

A low-swing clock double-edge triggered flip-flop

C. Kim, S. M. Kang

Research output: Contribution to conference › Paper › peer-review

Abstract

A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in clock network.

Original language	English
Pages	183-186
Number of pages	4
Publication status	Published - 2001
Externally published	Yes
Event	2001 VLSI Circuits Symposium - Kyoto, Japan Duration: 2001 Jun 14 → 2001 Jun 16

Other

Other	2001 VLSI Circuits Symposium
Country/Territory	Japan
City	Kyoto
Period	01/6/14 → 01/6/16

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A low-swing clock double-edge triggered flip-flop",

abstract = "A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in clock network.",

author = "C. Kim and Kang, {S. M.}",

year = "2001",

language = "English",

pages = "183--186",

note = "2001 VLSI Circuits Symposium ; Conference date: 14-06-2001 Through 16-06-2001",

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TY - CONF

T1 - A low-swing clock double-edge triggered flip-flop

AU - Kim, C.

AU - Kang, S. M.

PY - 2001

Y1 - 2001

N2 - A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in clock network.

AB - A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in clock network.

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M3 - Paper

AN - SCOPUS:0034794610

SP - 183

EP - 186

T2 - 2001 VLSI Circuits Symposium

Y2 - 14 June 2001 through 16 June 2001

ER -

A low-swing clock double-edge triggered flip-flop

Abstract

Other

ASJC Scopus subject areas

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