Abstract
A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in clock network.
| Original language | English |
|---|---|
| Pages | 183-186 |
| Number of pages | 4 |
| Publication status | Published - 2001 |
| Externally published | Yes |
| Event | 2001 VLSI Circuits Symposium - Kyoto, Japan Duration: 2001 Jun 14 → 2001 Jun 16 |
Other
| Other | 2001 VLSI Circuits Symposium |
|---|---|
| Country/Territory | Japan |
| City | Kyoto |
| Period | 01/6/14 → 01/6/16 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering