A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop

Byeong Chun So; Won Suk Hwang; Soo-Won Kim

doi:10.1109/EDSSC.2003.1283508

A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop

Byeong Chun So, Won Suk Hwang, Soo-Won Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25um CMOS technology. It is capable of recovering data at a speed of 2.5Gbps.

Original language	English
Title of host publication	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	171-174
Number of pages	4
ISBN (Print)	0780377494, 9780780377493
DOIs	https://doi.org/10.1109/EDSSC.2003.1283508
Publication status	Published - 2003
Event	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: 2003 Dec 16 → 2003 Dec 18

Other

Other	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country/Territory	Hong Kong
City	Tsimshatsui, Kowloon
Period	03/12/16 → 03/12/18

Keywords

Clock and Data Recovery(CDR)
Delay Locked Loop(DLL)
Low jitter
Multiphase
Phase detector
PLL

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2003.1283508

Cite this

A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop. / So, Byeong Chun; Hwang, Won Suk; Kim, Soo-Won.
2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 171-174 1283508.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

So, BC, Hwang, WS & Kim, S-W 2003, A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283508, Institute of Electrical and Electronics Engineers Inc., pp. 171-174, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 03/12/16. https://doi.org/10.1109/EDSSC.2003.1283508

@inproceedings{c3c91f7a5698478ab7498c3c41a8fc44,

title = "A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop",

abstract = "A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25um CMOS technology. It is capable of recovering data at a speed of 2.5Gbps.",

keywords = "Clock and Data Recovery(CDR), Delay Locked Loop(DLL), Low jitter, Multiphase, Phase detector, PLL",

author = "So, {Byeong Chun} and Hwang, {Won Suk} and Soo-Won Kim",

year = "2003",

doi = "10.1109/EDSSC.2003.1283508",

language = "English",

isbn = "0780377494",

pages = "171--174",

booktitle = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 ; Conference date: 16-12-2003 Through 18-12-2003",

}

TY - GEN

T1 - A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop

AU - So, Byeong Chun

AU - Hwang, Won Suk

AU - Kim, Soo-Won

PY - 2003

Y1 - 2003

N2 - A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25um CMOS technology. It is capable of recovering data at a speed of 2.5Gbps.

AB - A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25um CMOS technology. It is capable of recovering data at a speed of 2.5Gbps.

KW - Clock and Data Recovery(CDR)

KW - Delay Locked Loop(DLL)

KW - Low jitter

KW - Multiphase

KW - Phase detector

KW - PLL

UR - http://www.scopus.com/inward/record.url?scp=84946429487&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84946429487&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2003.1283508

DO - 10.1109/EDSSC.2003.1283508

M3 - Conference contribution

AN - SCOPUS:84946429487

SN - 0780377494

SN - 9780780377493

SP - 171

EP - 174

BT - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Y2 - 16 December 2003 through 18 December 2003

ER -

A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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