A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop

Byeong Chun So; Won Suk Hwang; Soo Won Kim

doi:10.1109/EDSSC.2003.1283508

A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop

Byeong Chun So
, Won Suk Hwang
, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25um CMOS technology. It is capable of recovering data at a speed of 2.5Gbps.

Original language	English
Title of host publication	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	171-174
Number of pages	4
ISBN (Electronic)	0780377494, 9780780377493
DOIs	https://doi.org/10.1109/EDSSC.2003.1283508
Publication status	Published - 2003
Event	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: 2003 Dec 16 → 2003 Dec 18

Publication series

Name	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Other

Other	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country/Territory	Hong Kong
City	Tsimshatsui, Kowloon
Period	03/12/16 → 03/12/18

Bibliographical note

Publisher Copyright:
©2003 IEEE.

Keywords

Clock and Data Recovery(CDR)
Delay Locked Loop(DLL)
Low jitter
Multiphase
PLL
Phase detector

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2003.1283508

Cite this

So, B. C., Hwang, W. S., & Kim, S. W. (2003). A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 171-174). Article 1283508 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283508

A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop. / So, Byeong Chun; Hwang, Won Suk; Kim, Soo Won.
2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 171-174 1283508 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

So, BC, Hwang, WS & Kim, SW 2003, A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283508, 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 171-174, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 03/12/16. https://doi.org/10.1109/EDSSC.2003.1283508

So BC, Hwang WS, Kim SW. A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 171-174. 1283508. (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). doi: 10.1109/EDSSC.2003.1283508

So, Byeong Chun ; Hwang, Won Suk ; Kim, Soo Won. / A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop. 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 171-174 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003).

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A multi-gigabit CMOS serial link transceiver using jitter tolerant delay locked loop

Abstract

Publication series

Other

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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