A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

Jaehun Jun; Jaegeun Song; Chulwoo Kim

doi:10.1109/TCSI.2017.2758793

A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

Jaehun Jun, Jaegeun Song, Chulwoo Kim

Research output: Contribution to journal › Article › peer-review

22 Citations (Scopus)

Abstract

A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 1020% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 1020% with a simply controlled body-biasing scheme compared with the conventional one.

Original language	English
Pages (from-to)	1567-1580
Number of pages	14
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	65
Issue number	5
DOIs	https://doi.org/10.1109/TCSI.2017.2758793
Publication status	Published - 2018 May

Bibliographical note

Funding Information:
This work was supported by the IT R&D Program of MOTIE/KEIT through Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC under Grant 10052716.

Funding Information:
Manuscript received March 29, 2017; revised August 14, 2017 and September 21, 2017; accepted September 24, 2017. Date of publication October 30, 2017; date of current version April 2, 2018. This work was supported by the IT R&D Program of MOTIE/KEIT through Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC under Grant 10052716. This paper was recommended by Associate Editor F. Kurdahi. (Corresponding author: Chulwoo Kim.) J. Jun is with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea, and also with the Circuit Research Division, LG Display, Paju 10845, South Korea.

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

CMOS integrated circuit
EDP
INWE
RSCE
digital cell library
energy efficiency
forward body biasing
near threshold voltage

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/TCSI.2017.2758793

Cite this

@article{335480601ee74993a0edd45fb77a6bd2,

title = "A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process",

abstract = "A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 1020% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 1020% with a simply controlled body-biasing scheme compared with the conventional one.",

keywords = "CMOS integrated circuit, EDP, INWE, RSCE, digital cell library, energy efficiency, forward body biasing, near threshold voltage",

author = "Jaehun Jun and Jaegeun Song and Chulwoo Kim",

note = "Funding Information: This work was supported by the IT R&D Program of MOTIE/KEIT through Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC under Grant 10052716. Funding Information: Manuscript received March 29, 2017; revised August 14, 2017 and September 21, 2017; accepted September 24, 2017. Date of publication October 30, 2017; date of current version April 2, 2018. This work was supported by the IT R&D Program of MOTIE/KEIT through Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC under Grant 10052716. This paper was recommended by Associate Editor F. Kurdahi. (Corresponding author: Chulwoo Kim.) J. Jun is with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea, and also with the Circuit Research Division, LG Display, Paju 10845, South Korea. Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2018",

month = may,

doi = "10.1109/TCSI.2017.2758793",

language = "English",

volume = "65",

pages = "1567--1580",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

AU - Jun, Jaehun

AU - Song, Jaegeun

AU - Kim, Chulwoo

N1 - Funding Information: This work was supported by the IT R&D Program of MOTIE/KEIT through Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC under Grant 10052716. Funding Information: Manuscript received March 29, 2017; revised August 14, 2017 and September 21, 2017; accepted September 24, 2017. Date of publication October 30, 2017; date of current version April 2, 2018. This work was supported by the IT R&D Program of MOTIE/KEIT through Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC under Grant 10052716. This paper was recommended by Associate Editor F. Kurdahi. (Corresponding author: Chulwoo Kim.) J. Jun is with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea, and also with the Circuit Research Division, LG Display, Paju 10845, South Korea. Publisher Copyright: © 2004-2012 IEEE.

PY - 2018/5

Y1 - 2018/5

N2 - A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 1020% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 1020% with a simply controlled body-biasing scheme compared with the conventional one.

AB - A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 1020% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 1020% with a simply controlled body-biasing scheme compared with the conventional one.

KW - CMOS integrated circuit

KW - EDP

KW - INWE

KW - RSCE

KW - digital cell library

KW - energy efficiency

KW - forward body biasing

KW - near threshold voltage

UR - http://www.scopus.com/inward/record.url?scp=85032744554&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2017.2758793

DO - 10.1109/TCSI.2017.2758793

M3 - Article

AN - SCOPUS:85032744554

SN - 1549-8328

VL - 65

SP - 1567

EP - 1580

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 5

ER -

A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this