A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

Jaehun Jun, Jaegeun Song, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)

Abstract

A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 1020% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 1020% with a simply controlled body-biasing scheme compared with the conventional one.

Original languageEnglish
Pages (from-to)1567-1580
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume65
Issue number5
DOIs
Publication statusPublished - 2018 May

Bibliographical note

Funding Information:
This work was supported by the IT R&D Program of MOTIE/KEIT through Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC under Grant 10052716.

Funding Information:
Manuscript received March 29, 2017; revised August 14, 2017 and September 21, 2017; accepted September 24, 2017. Date of publication October 30, 2017; date of current version April 2, 2018. This work was supported by the IT R&D Program of MOTIE/KEIT through Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC under Grant 10052716. This paper was recommended by Associate Editor F. Kurdahi. (Corresponding author: Chulwoo Kim.) J. Jun is with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea, and also with the Circuit Research Division, LG Display, Paju 10845, South Korea.

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

  • CMOS integrated circuit
  • EDP
  • INWE
  • RSCE
  • digital cell library
  • energy efficiency
  • forward body biasing
  • near threshold voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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