A new architecture for the fast viterbi algorithm

Inkyu Lee, Jeff L. Sonntag

Research output: Contribution to journalLetterpeer-review

18 Citations (Scopus)


A novel architecture design to speed up the Viterbi algorithm is proposed. By increasing the number of states in the trellis, the serial operation of a traditional add-compare-select unit is transformed into a parallel operation, thus achieving a substantial speed increase. The proposed architecture would increase the speed by 33% at the expense of a faily modest increase in area, thus becoming an attractive approach in high-speed applications. A simple example is shown to illustrate the proposed algorithm in maximum-likelihood sequence detector. A comparative synthesis is made to compare the proposed architecture with other approaches, and synthesis simulations confirm the projection of the throughput gain. Also, the proposed algorithm is extended to the block-processing architecture, and we show that an additional 50% speedup is achieved.

Original languageEnglish
Pages (from-to)1624-1628
Number of pages5
JournalIEEE Transactions on Communications
Issue number10
Publication statusPublished - 2003 Oct

Bibliographical note

Funding Information:
Paper approved by R. D. Wesel, the Editor for Coding and Communication Theory of the IEEE Communications Society. Manuscript received October 6, 2000; revised June 18, 2002. This work was supported in part by a Korea University grant, and in part by the Korea Science and Engineering Foundation under Grant R08-2003-000-10761-0.


  • Detector/decoder
  • Fast architecture
  • Viterbi algorithm (VA)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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