A new compact CMOS distributed digital attenuator

Kwangwon Park, Seungjong Lee, Sanggeun Jeon

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)

Abstract

This article presents a new millimeter-wave (mm-wave) distributed digital attenuator with a compact size and high linearity. To overcome the large area consumption of conventional distributed attenuators, multiple unit attenuation cells are combined at a single node, forming a multistate cell. By distributing the multistate cells along transmission lines (T-lines), the number of T-lines is reduced, leading to a compact chip size at a given attenuation range and step. The linearity is improved by stacking multiple FET varistors in each unit attenuation cell. An analytical analysis confirms that the proposed distributed attenuator topology maintains a low phase error comparable to that of the conventional counterpart. To experimentally verify the proposed topology, two different mm-wave digital attenuators are designed and implemented using a 65-nm CMOS technology. The first attenuator (Att1) uses a regular nFET as varistor of the attenuation cell, whereas the other attenuator (Att2_TW) uses a triple-well nFET to reduce the insertion loss. The maximum attenuation range of both attenuators is 14 dB with a step of 1 dB. The measured insertion losses of Att1 and Att2_TW are 4.8 and 4.1 dB at 35 GHz, respectively. The insertion losses are no more than 6.2 dB over 10-50 GHz and 4.3 dB over 15-43 GHz, respectively. The input 1-dB compression powers are 15 and 14 dBm, respectively, at 35 GHz. The chip sizes, excluding probing pads, are as small as 0.19 and 0.29 mm2.

Original languageEnglish
Article number9186068
Pages (from-to)4631-4640
Number of pages10
JournalIEEE Transactions on Microwave Theory and Techniques
Volume68
Issue number11
DOIs
Publication statusPublished - 2020 Nov

Bibliographical note

Funding Information:
ACKNOWLEDGMENT The authors would like to thank S. Park and H. Lee at Korea University for helpful discussion. The chip fabrication and EDA tool were supported by the IC Design Education Center.

Funding Information:
Manuscript received March 17, 2020; revised June 17, 2020 and July 21, 2020; accepted July 25, 2020. Date of publication September 3, 2020; date of current version November 4, 2020. This work was supported in part by Samsung Electronics and in part by the Ministry of Science and ICT (MSIT), South Korea, through the Information Technology Research Center (ITRC) Support Program supervised by the Institute of Information and Communications Technology Planning and Evaluation (IITP) under Grant IITP-2020-0-01749-001. (Corresponding author: Sanggeun Jeon.) Kwangwon Park was with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea. He is now with the Electronics and Communication Engineering, Republic of Korea Air Force Academy, Chungcheongbuk-do 28187, South Korea.

Publisher Copyright:
© 2020 IEEE.

Keywords

  • CMOS varistors
  • Digital attenuator
  • Distributed attenuator
  • Millimeter wave (mm-wave)
  • Multistate cell
  • Triple-well nFET

ASJC Scopus subject areas

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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