A novel architecture for block interleaving algorithm in MB-OFDM using Mixed Radix System

Youngsun Han, Peter Harliman, Seon Wook Kim, Jong Kook Kim, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)


In this paper, we present a novel architecture of a block interleaver in MB-OFDM systems based on Mixed Radix System (MRS). We prove mathematically that the proposed architecture can support bit permutations in the interleaving process. The hierarchical property of our proposed MRS-based design methodology allows the proposed architecture to support all the required data rates in the MB-OFDM systems with simple modular design. Furthermore, the same design to be used for the interleaver can also be used for the operation of de-interleaving, which reduces the implementation complexity significantly. The latency of our architecture is as low as 6 MB-OFDM symbols. In addition, when comparing our proposed architecture with the conventional approach, we are able to reduce the implementation complexity by 85.5%, 69.4%, and 40.3% for 80, 200, and 480 Mb/s data rates, respectively, while improving our operating maximum clock frequency by more than 3.3 times over the conventional design. We also show that the power consumption is reduced by 87.4%, 73.6%, and 39.8% for 80, 200, and 480 Mb/s, respectively.

Original languageEnglish
Article number5191026
Pages (from-to)1020-1024
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number6
Publication statusPublished - 2010 Jun

Bibliographical note

Funding Information:
Manuscript received April 14, 2008; revised October 24, 2008; accepted March 09, 2009. First published August 04, 2009; current version published May 26, 2010. This work was supported in part by the Ubiquitous Computing and Network (UCN) Project, Knowledge and Economy Frontier R&D Program of the Ministry of Knowledge Economy (MKE) in Korea as a result of UCN’s subproject 09C1-C2-30S, and by the University & Industrial Coordinate R&D Program of the Small and Medium Business Administration in Korea.


  • Array processor
  • Block interleaving
  • Mixed Radix System (MRS)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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